參數(shù)資料
型號(hào)： EVAL-ADUC832QSZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 30/92頁(yè)
文件大?。?/td> 0K
描述： KIT DEV FOR ADUC832 QUICK START
產(chǎn)品培訓(xùn)模塊： Process Control
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ 套件
類型： MCU
適用于相關(guān)產(chǎn)品： ADuC832
所含物品： 評(píng)估板，線纜，電源，軟件和文檔
其它名稱： EVAL-ADUC832QS
EVAL-ADUC832QS-ND
ADuC832
Data Sheet
Rev. B | Page 36 of 92
ADCCON1 (ADC Control SFR 1)
SFR Address:
EFH
SFR Power-On Default Value:
00H
Bit Addressable:
No
The ADCCON1 register controls conversion and acquisition
times, hardware conversion modes, and power-down modes as
detailed in Table 16.
Table 16. ADCCON1 SFR Bit Designations
Bit
Name
Description
[7]
MD1
The mode bit selects the active operating mode of the ADC. Set by the user to power up the ADC. Cleared by the user
to power down the ADC.
[6]
EXT_REF
Set by the user to select an external reference. Cleared by the user to use the internal reference.
[5]
CK1
The ADC clock divide bits (CK1, CK0) select the divide ratio for the PLL master clock used to generate the
[4]
CK0
ADC clock. To ensure correct ADC operation, the divider ratio must be chosen to reduce the ADC clock to ≤4.5 MHz. A
typical ADC conversion requires 17 ADC clocks. The divider ratio is selected as follows:
CK1
CK0
MCLK Divider
0
8
0
1
4
1
0
16
1
32
[3:2]
AQ[1:0]
The ADC acquisition select bits (AQ1, AQ0) select the time provided for the input track-and-hold amplifier to acquire
the input signal. An acquisition of three or more ADC clocks is recommended; clocks are selected as follows:
AQ1
AQ0
Number of ADC Clocks
0
1
0
1
2
1
0
3
1
4
[1]
T2C
The Timer 2 conversion bit (T2C) is set by the user to enable the Timer 2 overflow bit to be used as the ADC convert
start trigger input.
[0]
EXC
The external trigger enable bit (EXC) is set by the user to allow the external Pin P3.5/T1/CONVST to be used as the
active low convert start input. This input should be an active low pulse (minimum pulse width >100 ns) at the required
sample rate.
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