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| 型號： | EVAL-ADUC832QSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT DEV FOR ADUC832 QUICK START |
| 產(chǎn)品培訓(xùn)模塊： | Process Control |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuickStart™ 套件 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC832 |
| 所含物品： | 評估板，線纜，電源，軟件和文檔 |
| 其它名稱： | EVAL-ADUC832QS EVAL-ADUC832QS-ND |
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ADuC832
Data Sheet
Rev. B | Page 24 of 92
Pin No.
Mnemonic
MQFP
LFCSP
Type
Description
XTAL2
33
35
O
Output of the Inverting Oscillator Amplifier.
P2.4/A12/A20
36
39
I/O
Input/Output Port 2 (P2.4). Port 2 is a bidirectional port with internal pull-up resistors.
Port 2 pins that have 1s written to them are pulled high by the internal pull-up
resistors, and in that state can be used as inputs. As inputs, Port 2 pins being pulled
externally low sources current because of the internal pull-up resistors.
I/O
External Memory Addresses (A12/A20). Port 2 emits the high order address bytes
during fetches from external program memory and middle and high order address
bytes during accesses to the external 24-bit external data memory space.
P2.5/A13/A21
37
40
I/O
Input/Output Port 2 (P2.5). Port 2 is a bidirectional port with internal pull-up resistors.
Port 2 pins that have 1s written to them are pulled high by the internal pull-up
resistors, and in that state can be used as inputs. As inputs, Port 2 pins being pulled
externally low sources current because of the internal pull-up resistors.
I/O
External Memory Addresses (A13/A21). Port 2 emits the high order address bytes
during fetches from external program memory and middle and high order address
bytes during accesses to the external 24-bit external data memory space.
P2.6/PWM0/A14/A22
38
41
I/O
Input/Output Port 2 (P2.6). Port 2 is a bidirectional port with internal pull-up resistors.
Port 2 pins that have 1s written to them are pulled high by the internal pull-up
resistors, and in that state can be used as inputs. As inputs, Port 2 pins being pulled
externally low sources current because of the internal pull-up resistors.
O
PWM0 Voltage Output (PWM0). PWM outputs can be configured to use Port 2.6 and
Port 2.7 or Port 3.4 and Port 3.3
I/O
External Memory Addresses (A14/A22). Port 2 emits the high order address bytes
during fetches from external program memory and middle and high order address
bytes during accesses to the external 24-bit external data memory space.
P2.7/PWM1/A15/A23
39
42
I/O
Input/Output Port 2 (P2.7). Port 2 is a bidirectional port with internal pull-up resistors.
Port 2 pins that have 1s written to them are pulled high by the internal pull-up
resistors, and in that state can be used as inputs. As inputs, Port 2 pins being pulled
externally low sources current because of the internal pull-up resistors.
O
PWM1 Voltage Output (PWM1). See the ADuC832 Configuration SFR (CFG832) section
for further information.
I/O
External Memory Addresses (A15/A23). Port 2 emits the high order address bytes
during fetches from external program memory and middle and high order address
bytes during accesses to the external 24-bit external data memory space.
EA
40
43
I
External Access Enable, Logic Input. When held high, this input enables the device to
fetch code from internal program memory locations 0000H to 1FFFH. When held low,
this input enables the device to fetch all instructions from external program memory.
This pin should not be left floating.
PSEN
41
44
O
Program Store Enable, Logic Output. This output is a control signal that enables the
external program memory to the bus during external fetch operations. It is active
every six oscillator periods except during external data memory accesses. This pin
remains high during internal program execution. PSEN can also be used to enable
serial download mode when pulled low through a resistor on power-up or reset.
ALE
42
45
O
Address Latch Enable, Logic Output. This output is used to latch the low byte (and
page byte for 24-bit address space accesses) of the address into external memory
during normal operation. It is activated every six oscillator periods except during an
external data memory access.
P0.0/AD0
43
46
I/O
Input/Output Port 0 (P0.0). Port 0 is an 8-Bit Open-Drain Bidirectional I/O Port. Port 0
pins that have 1s written to them float and in that state can be used as high
impedance inputs.
I/O
External Memory Address and Data (AD0). Port 0 is also the multiplexed low order
address and data bus during accesses to external program or data memory. In this
application, it uses strong internal pull-ups when emitting 1s.
P0.1/AD1
44
47
I/O
Input/Output Port 0 (P0.1). Port 0 is an 8-Bit Open-Drain Bidirectional I/O Port. Port 0
pins that have 1s written to them float and in that state can be used as high
impedance inputs.
I/O
External Memory Address and Data (AD1). Port 0 is also the multiplexed low order
address and data bus during accesses to external program or data memory. In this
application, it uses strong internal pull-ups when emitting 1s.
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