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| 型號： | EVAL-ADUC832QSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 48/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT DEV FOR ADUC832 QUICK START |
| 產(chǎn)品培訓(xùn)模塊： | Process Control |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuickStart™ 套件 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC832 |
| 所含物品： | 評估板，線纜，電源，軟件和文檔 |
| 其它名稱： | EVAL-ADUC832QS EVAL-ADUC832QS-ND |
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ADuC832
Data Sheet
Rev. B | Page 52 of 92
USING THE DAC
The on-chip DAC architecture consists of a resistor string DAC
followed by an output buffer amplifier, the functional equivalent
of which is illustrated in Figure 51. Details of the actual DAC
architecture can be found in U.S. Patent Number 5,969,657.
Features of this architecture include inherent guaranteed
monotonicity and excellent differential linearity.
OUTPUT
BUFFER
HIGH Z
DISABLE
(FROM MCU)
DAC0
R
ADuC832
AVDD
VREF
0
29
87
-0
40
Figure 51. Resistor String DAC Functional Equivalent
As illustrated in Figure 51, the reference source for each DAC is
user selectable in software. It can be either AVDD or VREF. In 0 V
to AVDD mode, the DAC output transfer function spans from 0
V to the voltage at the AVDD pin. In 0 V to VREF mode, the DAC
output transfer function spans from 0 V to the internal VREF or,
if an external reference is applied, the voltage at the VREF pin.
The DAC output buffer amplifier features a true rail-to-rail
output stage implementation. This means that, unloaded, each
output is capable of swinging to within less than 100 mV of both
AVDD and ground. Moreover, the DAC’s linearity specification
(when driving a 10 kΩ resistive load to ground) is guaranteed
through the full transfer function except Code 0 to Code 100,
and, in 0 V to AVDD mode only, Code 3995 to Code 4095. Linearity
degradation near ground and AVDD is caused by saturation of
the output amplifier, and a general representation of its effects
(neglecting offset and gain error) is illustrated in Figure 52. The
dotted line in Figure 52 indicates the ideal transfer function,
and the solid line represents what the transfer function may
look like with endpoint nonlinearities due to saturation of the
output amplifier. Note that Figure 52 represents a transfer
function in 0 V to AVDD mode only. In 0 V to VREF mode (with
VREF < AVDD), the lower nonlinearity is similar, but the upper
portion of the transfer function follows the ideal line to the end
(VREF in this case, not AVDD), showing no signs of endpoint
linearity errors.
AVDD
AVDD –50mV
AVDD –100mV
100mV
50mV
0mV
000H
FFFH
02
987
-04
1
Figure 52. Endpoint Nonlinearities Due to Amplifier Saturation
The endpoint nonlinearities conceptually illustrated in Figure 52
become worse as a function of output loading. Most of the
ADuC832 specifications assume a 10 kΩ resistive load to
ground at the DAC output. As the output is forced to source or
sink more current, the nonlinear regions at the top or bottom
(respectively) of Figure 52 become larger. With larger current
demands, this can significantly limit output voltage swing.
Figure 53 and Figure 54 illustrate this behavior. It should be
noted that the upper trace in each of these figures is only valid
for an output range selection of 0 V to AVDD. In 0 V to VREF
mode, DAC loading does not cause high-side voltage drops as
long as the reference voltage remains below the upper trace in
the corresponding figure. For example, if AVDD = 3 V and VREF =
2.5 V, the high-side voltage is not affected by loads less than
5 mA. However, around 7 mA, the upper curve in Figure 54
drops below 2.5 V (VREF), indicating that, at these higher
currents, the output is not capable of reaching VREF.
SOURCE/SINK CURRENT (mA)
5
05
10
15
O
UT
P
UT
V
O
L
T
AG
E
(
V
)
4
3
2
1
0
DAC LOADED WITH 0000H
DAC LOADED WITH 0FFFH
02
98
7-
0
42
Figure 53. Source and Sink Current Capability with VREF = AVDD = 5 V
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