參數(shù)資料
型號： EVAL-ADUC7124QSPZ
廠商： Analog Devices Inc
文件頁數(shù)： 94/108頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR ADUC7124
設計資源： EVAL-ADUC7124 Schematic
ADUC7124 Eval Brd Gerber Files
標準包裝： 1
系列： MicroConverter® ADuC7xxx
類型： MCU
適用于相關(guān)產(chǎn)品： ADUC7124
所含物品： 板
ADuC7124/ADuC7126
Data Sheet
Rev. C | Page 86 of 108
FIQCLR Register
Name:
FIQCLR
Address:
0xFFFF010C
Default Value:
0x00000000
Access:
Write only
FIQSTA
FIQSTA is a read-only register that provides the current enabled
FIQ source status (effectively a logic AND of the FIQSIG and
FIQEN bits). When set to 1, that source generates an active FIQ
request to the ARM7TDMI core. There is no priority encoder
or interrupt vector generation. This function is implemented in
software in a common interrupt handler routine.
FIQSTA Register
Name:
FIQSTA
Address:
0xFFFF0100
Default Value:
0x00000000
Access:
Read only
Programmed Interrupts
Because the programmed interrupts are not maskable, they are
controlled by another register (SWICFG) that writes into the
IRQSTA and IRQSIG registers and/or the FIQSTA and FIQSIG
registers at the same time.
The 32-bit register dedicated to software interrupt is SWICFG
(described in Table 127). This MMR allows control of a pro-
grammed source interrupt.
Table 127. SWICFG MMR Bit Descriptions
Bit
Description
[31:3]
Reserved.
2
Programmed interrupt FIQ. Setting/clearing this bit
corresponds to setting/clearing Bit 1 of FIQSTA and
FIQSIG.
1
Programmed interrupt IRQ. Setting/clearing this bit
corresponds to setting/clearing Bit 1 of IRQSTA and
IRQSIG.
0
Reserved.
Any interrupt signal must be active for at least the minimum
interrupt latency time to be detected by the interrupt controller
and to be detected by the user in the IRQSTA/FIQSTA register.
INTERNAL
ARBITER
LOGIC
BITS[31:23]
UNUSED
BITS[22:7]
(IRQBASE)
BITS[6:2]
HIGHEST
PRIORITY
ACTIVE IRQ
BITS[1:0]
LSBs
IRQ_SOURCE
POINTER
FUNCTION
(IRQVEC)
FIQ_SOURCE
INTERRUPT VECTOR
PROGRAMMABLE PRIORITY
PER INTERRUT
(IRQP0/IRQP1/IRQP2/IRQP3)
09
12
3-
0
54
Figure 52. Interrupt Structure
VECTORED INTERRUPT CONTROLLER (VIC)
The ADUC7124/ADuC7126 incorporate an enhanced interrupt
control system or (vectored interrupt controller). The vectored
interrupt controller for IRQ interrupt sources is enabled by set-
ting Bit 0 of the IRQCONN register. Similarly, Bit 1 of IRQCONN
enables the vectored interrupt controller for the FIQ interrupt
sources. The vectored interrupt controller provides the following
enhancements to the standard IRQ/FIQ interrupts:
Vectored interrupts—allows a user to define separate
interrupt service routine addresses for every interrupt
source. This is achieved by using the IRQBASE and
IRQVEC registers.
IRQ/FIQ interrupts—can be nested up to eight levels
depending on the priority settings. An FIQ still has a
higher priority than an IRQ. Therefore, if the VIC is
enabled for both the FIQ and IRQ and prioritization is
maximized, it is possible to have 16 separate interrupt
levels.
Programmable interrupt priorities—using the IRQP0 to
IRQP3 registers, an interrupt source can be assigned an
interrupt priority level value between 0 and 7.
VIC MMRs
IRQBASE Register
The vector base register, IRQBASE, is used to point to the start
address of memory used to store 32 pointer addresses. These
pointer addresses are the addresses of the individual interrupt
service routines.
Name:
IRQBASE
Address:
0xFFFF0014
Default Value:
0x00000000
Access:
Read/write
Table 128. IRQBASE MMR Bit Descriptions
Bit
Type
Initial Value
Description
[31:16]
Read only
Reserved
Always read as 0.
[15:0]
R/W
0
Vector base address.
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