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參數(shù)資料
| 型號： | EVAL-ADF4193EBZ2 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION EB2 FOR ADF4193 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時，頻率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4193 |
| 主要屬性： | 400 MHz ~ 3.5 GHz，數(shù)字式可編程輸出相位 |
| 次要屬性： | 板不包括環(huán)路濾波器和 VCO |
| 已供物品： | 板，纜線，CD |
| 相關(guān)產(chǎn)品： | ADF4193BCPZ-ND - IC PLL FREQ SYNTHESIZER 32LFCSP ADF4193BCPZ-RL7-ND - IC PLL FREQ SYNTHESIZER 32LFCSP ADF4193BCPZ-RL-ND - IC PLL FREQ SYNTHESIZER 32LFCSP |
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Data Sheet
ADF4193
Rev. F | Page 13 of 32
Differential Amplifier
The internal, low noise, differential-to-single-ended amplifier is
used to convert the differential charge pump output to a single-
ended control voltage for the tuning port of the VCO. Figure 26
shows a simplified schematic of the differential amplifier. The
output voltage is equal to the differential voltage, offset by the
voltage on the CMR pin, according to
VAOUT = (VAIN+ VAIN) + VCMR
The CMR offset voltage is internally biased to three-fifths of
VP3, the differential amplifier power supply voltage, as shown in
Figure 26. Connect a 0.1 F capacitor to ground to the CMR pin
to roll off the thermal noise of the biasing resistors.
As can be seen in Figure 15, the differential amplifier output
voltage behaves according to the previous equation over a 4 V
range from approximately 1.2 V minimum up to VP3 0.3 V.
However, fast settling is guaranteed only over a tuning voltage
range from 1.8 V up to VP3 0.8 V. This is to allow sufficient
room for overshoot in the PLL frequency settling transient.
Noise from the differential amplifier is suppressed inside the
PLL bandwidth. For loop bandwidths >20 kHz, the 1/f noise has
a negligible effect on the PLL output phase noise. Outside the
loop bandwidth, the differential amplifier’s noise FM modulates
the VCO. The passive filter network following the differential
amplifier, shown in Figure 36, suppresses this noise contribution
to below the VCO noise from offsets of 400 kHz and above.
This network has a negligible effect on lock time because it is
bypassed when SW3 is closed while the loop is locking.
05328-
020
AIN–
AOUT
AIN+
CMR
VP3
C EXT =
0.1F
20k
30k
500
Figure 26. Differential Amplifier Block Diagram
MUXOUT and Lock Detect
The output multiplexer on the ADF4193 allows the user to
access various internal points on the chip. The state of MUXOUT
is controlled by M4 to M1 in the MUX register. Figure 35 shows
block diagram form.
05328-
021
R DIVIDER OUTPUT
N DIVIDER OUTPUT
SERIAL DATA OUTPUT
DGND
DVDD
CONTROL
MUX
MUXOUT
LOGIC LOW
THREE-STATE OUTPUT
TIMER OUTPUTS
DIGITAL LOCK DETECT
LOGIC HIGH
NOTE:
NOT ALL MUXOUT MODES SHOWN REFER TO MUX REGISTER
Figure 27. MUXOUT Circuit
Lock Detect
MUXOUT can be programmed to provide a digital lock detect
signal. Digital lock detect is active high. Its output goes high if
there are 40 successive PFD cycles with an input error of less
than 3 ns. For reliable lock detect operation with RF frequencies
<2 GHz, it is recommended that this threshold be increased to
10 ns by programming Register R6. The digital lock detect goes
low again when a new channel is programmed or when the
error at the PFD input exceeds 30 ns for one or more cycles.
Input Shift Register
The ADF4193 serial interface section includes a 24-bit input
shift register. Data is clocked in MSB first on each rising edge
of CLK. Data from the shift register is latched into one of eight
control registers, R0 to R7, on the rising edge of latch enable
(LE). The destination register is determined by the state of
the three control bits (Control Bit C3, Control Bit C2, and
Control Bit C1) in the shift register. The three LSBs are Bit DB2,
Bit DB1, and Bit DB0, as shown in the timing diagram of Figure 2.
The truth table for these bits is shown in Table 5. Figure 28
shows a summary of how the registers are programmed.
Table 5. C3, C2, and C1 Truth Table
Control Bits
C3
C2
C1
Name
Register
0
FRAC/INT
R0
0
1
MOD/R
R1
0
1
0
Phase
R2
0
1
Function
R3
1
0
Charge Pump
R4
1
0
1
Power-Down
R5
1
0
Mux
R6
1
Test Mode
R7
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