R
參數(shù)資料
型號(hào)： EVAL-ADF4193EBZ2
廠商： Analog Devices Inc
文件頁數(shù)： 27/32頁
文件大?。?/td> 0K
描述： BOARD EVALUATION EB2 FOR ADF4193
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，頻率合成器
嵌入式： 否
已用 IC / 零件： ADF4193
主要屬性： 400 MHz ~ 3.5 GHz，數(shù)字式可編程輸出相位
次要屬性： 板不包括環(huán)路濾波器和 VCO
已供物品： 板，纜線，CD
相關(guān)產(chǎn)品： ADF4193BCPZ-ND - IC PLL FREQ SYNTHESIZER 32LFCSP
ADF4193BCPZ-RL7-ND - IC PLL FREQ SYNTHESIZER 32LFCSP
ADF4193BCPZ-RL-ND - IC PLL FREQ SYNTHESIZER 32LFCSP
ADF4193
Data Sheet
Rev. F | Page 4 of 32
Parameter
B Version1
CVersion2
Unit
Test Conditions/Comments
SW1, SW2, and SW3
RON (SW1 and SW2)
65
typ
RON SW3
75
typ
NOISE CHARACTERISTICS
Output
900 MHz4
108
dBc/Hz typ
At 5 kHz offset and 26 MHz PFD frequency
1800 MHz5
102
dBc/Hz typ
At 5 kHz offset and 13 MHz PFD frequency
Phase Noise
Normalized Phase Noise
Floor (PNSYNTH)6
216
dBc/Hz typ
At VCO output with dither off, PLL loop
bandwidth = 500 kHz
Normalized 1/f Noise (PN1_f)7
110
dBc/Hz typ
Measured at 10 kHz offset, normalized to 1 GHz
1
Operating temperature range is from 40°C to +85°C.
2
Operating temperature range is from 40°C to +105°C
3
The prescaler value is chosen to ensure that the RF input is divided down to a frequency that is less than this value.
4
fREFIN = 26 MHz; fSTEP = 200 kHz; fRF = 900 MHz; loop bandwidth = 40 kHz.
5
fREFIN = 13 MHz; fSTEP = 200 kHz; fRF = 1800 MHz; loop bandwidth = 60 kHz.
6
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider
value) and 10 log(fPFD). PNSYNTH = PNTOT 10 log(fPFD) 20 log(N).
7
The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency,
fRF, and at an offset frequency, f, is given by PN = P1_f+ 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in
ADIsimPLL.
TIMING CHARACTERISTICS
AVDD = DVDD = 3 V ± 10%, VP1, VP2 = 5 V ± 10%, VP3 = 5.35 V ± 5%, AGND = DGND = GND = 0 V, RSET = 2.4 k, dBm referred to
50 , TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
Limit (B Version)1
Limit (C Version) 2
Unit
Test Conditions/Comments
t1
10
ns min
LE setup time
t2
10
ns min
DATA to CLOCK setup time
t3
10
ns min
DATA to CLOCK hold time
t4
15
ns min
CLOCK high duration
t5
15
ns min
CLOCK low duration
t6
10
ns min
CLOCK to LE setup time
t7
15
ns min
LE pulse width
1
Operating temperature is from 40°C to +85°C.
2
Operating temperature is from 40°C to +105°C.
05238-
002
CLK
DATA
DB23
(MSB)
DB22
DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
LE
t2
t4
t5
t3
t7
t6
t1
Figure 2. Timing Diagram
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