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參數(shù)資料
| 型號： | EVAL-ADF4193EBZ2 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/32頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION EB2 FOR ADF4193 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計時，頻率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4193 |
| 主要屬性： | 400 MHz ~ 3.5 GHz，數(shù)字式可編程輸出相位 |
| 次要屬性： | 板不包括環(huán)路濾波器和 VCO |
| 已供物品： | 板，纜線，CD |
| 相關(guān)產(chǎn)品： | ADF4193BCPZ-ND - IC PLL FREQ SYNTHESIZER 32LFCSP ADF4193BCPZ-RL7-ND - IC PLL FREQ SYNTHESIZER 32LFCSP ADF4193BCPZ-RL-ND - IC PLL FREQ SYNTHESIZER 32LFCSP |
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Data Sheet
ADF4193
Rev. F | Page 19 of 32
CHARGE PUMP REGISTER (R4)
05328-
027
DB23
0
DB22
0
DB21
0
DB20
0
DB19
0
DB18
0
DB17
0
DB16
0
DB15
0
DB14
1
DB13
C9
DB12
C8
DB11
C7
DB10
C6
DB9
C5
DB8
C4
DB7
C3
DB6
C2
DB5
C1
DB4
F2
DB3
F1
DB2
C3 (1)
DB1
C2 (0)
DB0
C1 (0)
9-BIT TIMEOUT COUNTER
RESERVED
CONTROL
BITS
TIMER
SELECT
0
1
F2
0
1
0
1
F1
SW1/SW2
SW3
ICP
NOT USED
TIMER SELECT
C9
0
.
1
C8
0
.
1
C7
0
.
1
..........
C3
0
.
1
C2
0
1
.
0
1
C1
0
1
0
1
.
0
1
0
1
TIMEOUT COUNTER
0
1
2
3
.
508
509
510
511
xPFD CYCLES
0
4
8
12
.
2032
2036
2040
2044
DELAY s1
0
0.15
0.30
0.46
.
78.15
78.30
78.46
78.61
1DELAY WITH 26MHz PFD
Figure 33. Charge Pump Register (R4)
Reserved Bits
Bit DB23 to Bit DB14 are reserved and should be set to hex
code 001 for normal operation.
9-Bit Timeout Counter
These bits are used to program the fast lock timeout counters.
The counters are clocked at one-quarter the PFD reference
frequency, therefore, their time delay scales with the PFD
frequency according to
Delay(s) = (Timeout Counter Value × 4)/(PFD Frequency)
For example, if 35 were loaded with timer select (00) with a
13 MHz PFD, then SW1/SW2 would be switched after
(35 × 4)/13 MHz = 10.8 s
Timer Select
These two address bits select the timeout counter to be
programmed. Note that to set up the ADF4193 correctly
requires setup of these three timeout counters; therefore, three
writes to this register are required in the initialization sequence.
Table 6 shows example values for a GSM Tx synthesizer with a
60 kHz final loop BW. See the Applications section for more
information.
Table 6. Recommended Values for a GSM Tx LO
Timer Select
Timeout Counter
Value
Time (s) with
PFD = 13 MHz
10
ICP
28
8.6
01
SW1/2
35
10.8
00
SW3
35
10.8
On each write to R0, the timeout counters start. Switch SW3
closes until the SW3 counter times out. Similarly, switches
SW1/SW2 close until the SW1/SW2 counter times out. When
the ICP counter times out, the charge pump current is ramped
down from 64× to 1× in six binary steps. It is recommended
that the SW1, SW2, and SW3 timeout counter values are set
equal to the ICP timeout counter value plus 7, as in the example
of Table 6.
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