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參數(shù)資料
| 型號(hào)： | EVAL-ADF4193EBZ2 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 30/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION EB2 FOR ADF4193 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，頻率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4193 |
| 主要屬性： | 400 MHz ~ 3.5 GHz，數(shù)字式可編程輸出相位 |
| 次要屬性： | 板不包括環(huán)路濾波器和 VCO |
| 已供物品： | 板，纜線，CD |
| 相關(guān)產(chǎn)品： | ADF4193BCPZ-ND - IC PLL FREQ SYNTHESIZER 32LFCSP ADF4193BCPZ-RL7-ND - IC PLL FREQ SYNTHESIZER 32LFCSP ADF4193BCPZ-RL-ND - IC PLL FREQ SYNTHESIZER 32LFCSP |
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Data Sheet
ADF4193
Rev. F | Page 7 of 32
Pin No.
Mnemonic
Description
23
RSET
Connecting a resistor between this pin and GND sets the charge pump output current. The nominal voltage bias at
the RSET pin is 0.55 V. The relationship between ICP and RSET is
ICP = 0.25/RSET
So, with RSET = 2.4 k, ICP = 104 A.
24
VP2
Power Supply Pin for the Charge Pump. Nominally 5 V, should be at the same voltage at VP1. A 0.1 F decoupling
capacitor to ground should be placed as close as possible to this pin.
25
AIN
Differential Amplifier’s Negative Input Pin.
26
CPOUT
Differential Charge Pump’s Negative Output Pin. Should be connected to AIN and the loop filter.
27
SW2
Fast Lock Switch 2. This switch is closed to SWGND while the SW1/SW2 timeout counter is active.
28
SWGND
Common for SW1 and SW2 Switches. Should be connected to the ground plane.
29
SW1
Fast Lock Switch 1. This switch is closed to SWGND while the SW1/SW2 timeout counter is active.
30
CPOUT+
Differential Charge Pump’s Positive Output Pin. Should be connected to AIN+ and the loop filter.
31
AIN+
Differential Amplifier’s Positive Input Pin.
32
VP3
Power Supply Pin for the Differential Amplifier. This can range from 5.0 V to 5.5 V. A 0.1 F decoupling capacitor to
ground should be placed as close as possible to this pin. Also requires a 10 F decoupling capacitor to ground.
EP
Exposed Pad. The exposed pad must be connected to AGND.
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