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參數(shù)資料
| 型號(hào)： | EVAL-ADF4153EBZ1 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 14/24頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADF4153 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，頻率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4153 |
| 主要屬性： | 單路分?jǐn)?shù)-N PLL |
| 次要屬性： | 1.75GHz 圖形用戶界面 |
| 已供物品： | 板，線纜，軟件 |
| 相關(guān)產(chǎn)品： | ADF4153WYRUZ-RL7TR-ND - IC SYNTH PLL RF F-N FREQ 16TSSOP ADF4153YRUZ-RL7-ND - IC SYNTH FRACT-N FREQ 16-TSSOP ADF4153YRUZ-RL-ND - IC SYNTH FRACT-N FREQ 16-TSSOP ADF4153YCPZ-RL7-ND - IC SYNTH FRACT-N FREQ 20-LFCSP ADF4153YCPZ-RL-ND - IC SYNTH FRACT-N FREQ 20-LFCSP ADF4153YCPZ-ND - IC SYNTH FRACT-N FREQ 20-LFCSP ADF4153YRUZ-ND - IC SYNTH PLL RF F-N FREQ 16TSSOP ADF4153BCPZ-RL7-ND - IC FRACTION-N FREQ SYNTH 20LFCSP ADF4153BRUZ-RL7-ND - IC FRACTION-N FREQ SYNTH 16TSSOP ADF4153BCPZ-RL-ND - IC FRACTION-N FREQ SYNTH 20LFCSP 更多... |
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Data Sheet
ADF4153
Rev. F | Page 21 of 24
When operating in this mode, the maximum SCLOCK rate of
the ADuC812 is 4 MHz. This means that the maximum rate at
which the output frequency can be changed is 180 kHz.
ADSP-21xx Interface
Figure 19 shows the interface between the ADF4153 and the
ADSP-21xx digital signal processor. As discussed previously,
the ADF4153 needs a 24-bit serial word for each latch write.
The easiest way to accomplish this using the ADSP-21xx family
is to use the autobuffered transmit mode of operation with
alternate framing. This provides a means for transmitting an
entire block of serial data before an interrupt is generated.
Set up the word length for eight bits and use three memory
locations for each 24-bit word. To program each 24-bit latch,
store the three 8-bit bytes, enable the autobuffered mode, and
write to the transmit register of the DSP. This last operation
initiates the autobuffer transfer.
ADSP-21xx
ADF4153
SCLK
CLK
DATA
LE
MUXOUT
(LOCK DETECT)
DT
TFS
I/O FLAGS
03685-
025
Figure 19. ADSP-21xx to ADF4153 Interface
PCB DESIGN GUIDELINES FOR CHIP SCALE
PACKAGE
The lands on the chip scale package (CP-20) are rectangular.
The printed circuit board (PCB) pad for these should be 0.1 mm
longer than the package land length and 0.05 mm wider than
the package land width. The land should be centered on the
pad. This ensures that the solder joint size is maximized.
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the PCB should be at least as large as this
exposed pad. On the PCB, there should be a clearance of at least
0.25 mm between the thermal pad and the inner edges of the
pad pattern. This ensures that shorting is avoided.
Thermal vias can be used on the PCB thermal pad to improve
thermal performance of the package. If vias are used, they should
be incorporated in the thermal pad at 1.2 mm pitch grid. The
via diameter should be between 0.3 mm and 0.33 mm, and the
via barrel should be plated with one ounce of copper to plug the
via. The user should connect the PDB thermal pad to AGND.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| EVAL-ADF4154EB1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Fractional-N Frequency Synthesizer |
| EVAL-ADF4154EBZ1 | 功能描述:BOARD EVALUATION FOR ADF4154EB1 RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| EVAL-ADF4156EBZ1 | 制造商:Analog Devices 功能描述:EVAL BOARD - Bulk |
| EVAL-ADF4157EB1Z | 功能描述:BOARD EVALUATION FOR ADF4157 RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| EVAL-ADF4157EB1Z1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Resolution 6 GHz Fractional-N Frequency Synthesizer |
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