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參數(shù)資料
| 型號： | EVAL-ADF4007EBZ1 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/16頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADF4007EB1 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計時，頻率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4007 |
| 主要屬性： | 單路整數(shù)-N PLL |
| 次要屬性： | 7.5GHz |
| 已供物品： | 板，纜線，CD |
| 相關(guān)產(chǎn)品： | ADF4007BCPZ-ND - IC DIVIDER/PLL SYNTHESZR 20LFCSP ADF4007BCPZ-RL7-ND - IC DIVIDER/PLL SYNTHESZR 20LFCSP ADF4007BCPZ-RL-ND - IC DIVIDER/PLL SYNTHESZR 20LFCSP |
| 其它名稱： | Q5364837 |
Data Sheet
ADF4007
Rev. B | Page 9 of 16
THEORY OF OPERATION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 9. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
100k
NC
REFIN
NC
NO
SW1
SW2
BUFFER
SW3
TO R COUNTER
POWER-DOWN
CONTROL
04537-
015
Figure 9. Reference Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 10. It is followed by a
2-stage limiting amplifier to generate the CML clock levels
needed for the prescaler.
500
1.6V
500
AGND
BIAS
GENERATOR
RFINA
RFINB
AVDD
04537-
016
Figure 10. RF Input Stage
PRESCALER P
The prescaler, operating at CML levels, takes the clock from the
RF input stage and divides it down to a manageable frequency
for the PFD. The prescaler can be selected to be either 8, 16, 32,
or 64, and is effectively the N value in the PLL synthesizer. The
terms N and P are used interchangeably in this data sheet. N1
and N2 set the prescaler values. The prescaler value should be
chosen so that the prescaler output frequency is always less than
or equal to 120 MHz, the maximum specified PFD frequency.
Thus, with an RF frequency of 4 GHz, a prescaler value of 64 is
valid, but a value of 32 or less is not valid.
2
]
[
REFIN
VCO
f
N
f
×
=
R COUNTER
The R counter is permanently set to 2. It allows the input reference
frequency to be divided down by 2 to produce the reference clock
to the phase frequency detector (PFD).
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and the N counter
(prescaler, P) and produces an output proportional to the phase
and frequency difference between them. Figure 11 is a simplified
schematic. The PFD includes a fixed, 3 ns delay element that
controls the width of the antibacklash pulse. This pulse ensures
that there is no dead zone in the PFD transfer function and
minimizes phase noise and reference spurs.
LOGIC HI
D1
D2
Q1
Q2
CLR1
CLR2
CP
U1
U2
UP
DOWN
CPGND
U3
R DIVIDER
3ns
DELAY
N DIVIDER
VP
CHARGE
PUMP
04537-
017
LOGIC HI
Figure 11. PFD Simplified Schematic and Timing (In Lock)
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