參數(shù)資料
型號: EVAL-ADF4007EBZ1
廠商: Analog Devices Inc
文件頁數(shù): 12/16頁
文件大小: 0K
描述: BOARD EVALUATION FOR ADF4007EB1
標(biāo)準(zhǔn)包裝: 1
主要目的: 計時,頻率合成器
嵌入式:
已用 IC / 零件: ADF4007
主要屬性: 單路整數(shù)-N PLL
次要屬性: 7.5GHz
已供物品: 板,纜線,CD
相關(guān)產(chǎn)品: ADF4007BCPZ-ND - IC DIVIDER/PLL SYNTHESZR 20LFCSP
ADF4007BCPZ-RL7-ND - IC DIVIDER/PLL SYNTHESZR 20LFCSP
ADF4007BCPZ-RL-ND - IC DIVIDER/PLL SYNTHESZR 20LFCSP
其它名稱: Q5364837
Data Sheet
ADF4007
Rev. B | Page 5 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
14
13
12
1
3
4
M1
15 MUXOUT
M2
N1
11 N2
CPGND
NOTES
1. THE LFCSP HAS AN EXPOSED PADDLE THAT
MUST BE CONNECTED TO GROUND.
AGND
2
AGND
RFINB
5
RFINA
7
A
V
DD
6
A
V
DD
8
RE
F
IN
9
DG
ND
10
DG
ND
19
R
SET
20
C
P
18
V
P
17
DV
DD
16
DV
DD
TOP
VIEW
ADF4007
04537-
002
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
CPGND
Charge Pump Ground. The ground return path of the charge pump.
2, 3
AGND
Analog Ground. The ground return path of the prescaler.
4
RF
INB
Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a small bypass
capacitor, typically 100 pF.
5
RF
INA
Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.
6, 7
AV
DD
Analog Power Supply. This pin can range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin. AV
DD must be the same value as DVDD.
8
REF
IN
Reference Input. A CMOS input with a nominal threshold of V
DD/2 and a dc equivalent input resistance of 100 k.
This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
9, 10
DGND
Digital Ground.
11, 12
N2, N1
These two bits set the N value. See Table 4.
13, 14
M2, M1
These two bits set the status of MUXOUT and PFD polarity. See Table 5.
15
MUXOUT
This multiplexer output allows either the N divider output or the R divider output to be accessed externally.
16, 17
DV
DD
Digital Power Supply. This pin can range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground plane
should be placed as close as possible to this pin. DV
DD must be the same value as AVDD.
18
V
P
Charge Pump Power Supply. This pin should be greater than or equal to V
DD. In systems where VDD is 3 V, it can be
set to 5 V and used to drive a VCO with a tuning range of up to 5 V.
19
R
SET
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The nominal
voltage potential at the R
SET pin is 0.66 V. The relationship between ICP and RSET is
SET
MAX
CP
R
I
5
.
25
=
Therefore, if R
SET = 5.1 k, then ICP = 5 mA.
20
CP
Charge Pump Output. When enabled, this pin provides ±I
CP to the external loop filter, which in turn drives the
external VCO.
21
EP
Exposed Pad.
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