- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16522 > EVAL-ADAU1781Z (Analog Devices Inc)BOARD EVAL FOR ADAU1781 PDF資料下載
參數(shù)資料
| 型號： | EVAL-ADAU1781Z |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 30/92頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADAU1781 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SigmaDSP® |
| 主要目的： | 音頻編解碼器 |
| 嵌入式： | 是，DSP |
| 已用 IC / 零件： | ADAU1781 |
| 主要屬性： | 立體聲，24 位，8 ~ 96 kHz 采樣率，GUI 工具 |
| 次要屬性： | * |
| 已供物品： | * |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁當(dāng)前第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁
ADAU1781
Rev. B | Page 36 of 92
SPI PORT
By default, the ADAU1781 is in I2C mode, but can be put into SPI
control mode by pulling CLATCH low three times. The SPI port
uses a 4-wire interface, consisting of CLATCH, CCLK, CDATA,
and COUT signals, and is always a slave port. The CLATCH
Chip Address R/
signal
goes low at the beginning of a transaction and high at the end of
a transaction. The CCLK signal latches CDATA on a low-to-high
transition. COUT data is shifted out of the ADAU1781 on the
falling edge of CCLK and should be clocked into a receiving
device, such as a microcontroller, on the CCLK rising edge. The
CDATA signal carries the serial input data, and the COUT signal is
the serial output data. The COUT signal remains three-stated until
a read operation is requested. This allows other SPI-compatible
peripherals to share the same readback line. All SPI transactions
have the same basic format shown in Table 24. A timing diagram
is shown in Figure 4. All data should be written MSB first. The
ADAU1781 can be taken out of SPI mode only by a full reset.
W
The first byte of an SPI transaction includes the 7-bit chip address
and an R/W
Table 23. SPI Address Byte Format
bit. The chip address is always 0x38. The LSB of
this first byte determines whether the SPI transaction is a read
(Logic 1) or a write (Logic 0).
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
0
R/W
Subaddress
The 12-bit subaddress word is decoded into a location in one of
the registers. This subaddress is the location of the appropriate
register. The MSBs of the subaddress are zero-padded to bring the
word to a full 2-byte length.
Data Bytes
The number of data bytes varies according to the register being
accessed. During a burst mode write, an initial subaddress is
written followed by a continuous sequence of data for consecutive
register locations. A sample timing diagram for a single-write
SPI operation to the parameter memory is shown in Figure 43.
A sample timing diagram of a single-read SPI operation is shown in
Figure 44. The COUT pin goes from three-state to being driven at
the beginning of Byte 3. In this example, Byte 0 to Byte 2 contain
the addresses and R/W
SPI Read/Write Clock Frequency (CCLK)
bit, and subsequent bytes carry the data.
The SPI port of the ADAU1781 has asymmetrical read and
write clock frequencies. It is possible to write data into the
device at higher data rates than reading data out of the device.
More detailed information is available in the Digital Timing
Specifications section.
MEMORY AND REGISTER ACCESS
Several conditions must be true to have full access to all memory
and registers via the control port:
The ADAU1781 must have finished its initialization,
including power-on reset, PLL lock, and self-boot.
The core clock must be enabled (Register 16384 (0x4000),
clock control, Bit 0, core clock enable, set to 1).
The memory controller must be powered (Register 16512
(0x4080), Digital Power-Down 0, Bit 6, memory controller,
set to 1).
The SigmaDSP core must be powered (Register 16512
(0x4080), Digital Power-Down 0, Bit 0, SigmaDSP core,
set to 1).
Table 24. Generic Control Word Format
Byte 0
Byte 1
Byte 2
Byte 3
Byte 41
CHIP_ADR[6:0], R/W
SUBADR[15:8]
SUBADR[7:0]
Data
1 Continues to end of data.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MCP1316T-46BE/OT | IC SPRVSR SMPL RSET 4.6V SOT23-5 |
| EBM28DTBN-S189 | CONN EDGECARD 56POS R/A .156 SLD |
| 6374110-4 | C/A SM, LC TO LC 4METER |
| EBM28DTBH-S189 | CONN EDGECARD 56POS R/A .156 SLD |
| VI-J0F-EZ-S | CONVERTER MOD DC/DC 72V 25W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-ADAU1962AZ | 制造商:Analog Devices 功能描述:EVAL BOARD FOR ADAU1962A - Boxed Product (Development Kits) 制造商:Analog Devices 功能描述:Eval Board for ADAU1962A |
| EVAL-ADAU1966AZ | 制造商:Analog Devices 功能描述:EVAL BOARD FOR ADAU1962A - Boxed Product (Development Kits) |
| EVAL-ADAU1966Z | 功能描述:BOARD EVAL FOR ADAU1966 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| EVAL-ADAU1966Z | 制造商:Analog Devices 功能描述:ADAU1966, DAC, SIGMA DELTA, SPI, I2C, EV |
| EVAL-ADAU1978Z | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad Analog-to-Digital Converter (ADC) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。