參數(shù)資料
型號： EVAL-AD7666CBZ
廠商： Analog Devices Inc
文件頁數(shù)： 16/28頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD7666
標(biāo)準(zhǔn)包裝： 1
系列： PulSAR®
ADC 的數(shù)量： 1
位數(shù)： 16
采樣率（每秒）： 500k
數(shù)據(jù)接口： 串行，并聯(lián)
輸入范圍： ±VREF
在以下條件下的電源（標(biāo)準(zhǔn)）： 81mW @ 500kSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD7666
已供物品： 板
相關(guān)產(chǎn)品： AD7666ACPZ-ND - IC ADC 16BIT UNIPOLAR 48LFCSP
AD7666ASTZ-ND - IC ADC 16BIT UNIPOLAR 48LQFP
AD7666ACPZRL-ND - IC ADC 16BIT UNIPOLAR 48LFCSP
AD7666ASTZRL-ND - IC ADC 16BIT UNIPOLAR 48LQFP
AD7666
Rev. 0 | Page 23 of 28
MASTER SERIAL INTERFACE
Usually, because the AD7666 is used with a fast throughput, the
Master Read During Conversion mode is the most recommen-
ded serial mode. In this mode, the serial clock and data toggle at
appropriate instants, minimizing potential feedthrough between
digital activity and critical conversion decisions.
Internal Clock
The AD7666 is configured to generate and provide the serial
data clock SCLK when the EXT/INT pin is held LOW. The
AD7666 also generates a SYNC signal to indicate to the host
when the serial data is valid. The serial clock SCLK and the
SYNC signal can be inverted if desired. Depending on the
RDC/SDIN input, the data can be read after each conversion or
during the following conversion. Figure 39 and Figure 40 show
detailed timing diagrams of these two modes.
In Read After Conversion mode, it should be noted that unlike
in other modes, the BUSY signal returns LOW after the 16 data
bits are pulsed out and not at the end of the conversion phase,
which results in a longer BUSY width.
t3
BUSY
SYNC
SCLK
SDOUT
t28
t29
t14
t18
t19
t20
t21
t24
t26
t27
t23
t22
t16
t15
12
3
14
15
16
D15
D14
D2
D1
D0
X
RDC/SDIN = 0
INVSCLK = INVSYNC = 0
t25
t30
03033-0-032
CNVST
CS, RD
EXT/INT = 0
Figure 39. Master Serial Data Timing for Reading (Read after Convert)
EXT/INT = 0
RDC/SDIN = 1
INVSCLK = INVSYNC = 0
t3
t1
t17
t14
t19
t20 t21
t24
t26
t25
t27
t23
t22
t16
t15
D15
D14
D2
D1
D0
X
12
3
14
15
16
t
18
BUSY
SYNC
SCLK
SDOUT
03033-0-033
CNVST
CS, RD
Figure 40. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)
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