I2C TIMING SPECIFICATIONS
參數(shù)資料
型號： EVAL-AD7291SDZ
廠商： Analog Devices Inc
文件頁數(shù)： 26/29頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD7291
標準包裝： 1
ADC 的數(shù)量： 8
位數(shù)： 12
采樣率（每秒）： 22.22k
數(shù)據(jù)接口： I²C
已用 IC / 零件： AD7291
已供物品： 板
相關(guān)產(chǎn)品： AD7291BCPZ-RL7-ND - IC ADC I2C/SRL 22.22K 20LFCSP
AD7291BCPZ-ND - IC ADC 12BIT SAR 8CH 20-LFCSP
Data Sheet
AD7291
Rev. B | Page 5 of 28
I2C TIMING SPECIFICATIONS
Guaranteed by initial characterization. All values were measured with the input filtering enabled. CB refers to the capacitive load on the
bus line, with tR and tF measured between 0.3 × VDRIVE and 0.7 × VDRIVE (see Figure 2). VDD = 2.8 V to 3.6 V; VDRIVE = 1.65 V to 3.6 V; VREF =
2.5 V internal/external; TA = 40°C to +125°C, unless otherwise noted.
Table 3.
Limit at TMIN, TMAX
Parameter
Conditions
Min
Typ
Max
Unit
Description
fSCL
Standard mode
100
kHz
Serial clock frequency
Fast mode
400
kHz
t1
Standard mode
4
μs
tHIGH, SCL high time
Fast mode
0.6
μs
t2
Standard mode
4.7
μs
tLOW, SCL low time
Fast mode
1.3
μs
t3
Standard mode
250
ns
tSU;DAT, data setup time
Fast mode
100
ns
Standard mode
0
3.45
μs
tHD;DAT, data hold time
Fast mode
0
0.9
μs
t5
Standard mode
4.7
μs
tSU;STA, setup time for a repeated start condition
Fast mode
0.6
μs
t6
Standard mode
4
μs
tHD;STA, hold time for a repeated start condition
Fast mode
0.6
μs
t7
Standard mode
4.7
μs
tBUF, bus-free time between a stop and a start condition
Fast mode
1.3
μs
t8
Standard mode
4
μs
tSU;STO, setup time for a stop condition
Fast mode
0.6
μs
t9
Standard mode
1000
ns
tRDA, rise time of the SDA signal
Fast mode
20 + 0.1 CB
300
ns
t10
Standard mode
300
ns
tFDA, fall time of the SDA signal
Fast mode
20 + 0.1 CB
300
ns
t11
Standard mode
1000
ns
tRCL, rise time of the SCL signal
Fast mode
20 + 0.1 CB
300
ns
t11A
Standard mode
1000
ns
tRCL1, rise time of the SCL signal after a repeated
Fast mode
20 + 0.1 CB
300
ns
start condition and after an acknowledge bit
t12
Standard mode
300
ns
tFCL, fall time of the SCL signal
Fast mode
20 + 0.1 CB
300
ns
tSP
Fast mode
0
50
ns
Pulse width of the suppressed spike
tPOWER-UP
6
ms
Power-up and acquisition time
1 A device must provide a data hold time for SDA to bridge the undefined region of the SCL falling edge.
t6
t7
t2
t11
t4
t1
t12
t10
t5
t9
t6
t3
t8
0
87
11
-0
02
SCL
S
SDA
S = START CONDITION
P = STOP CONDITION
P
S
Figure 2. 2-Wire Serial Interface Timing Diagram
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