參數(shù)資料
型號(hào)： EVAL-AD7291SDZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 10/29頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD7291
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 8
位數(shù)： 12
采樣率（每秒）： 22.22k
數(shù)據(jù)接口： I²C
已用 IC / 零件： AD7291
已供物品： 板
相關(guān)產(chǎn)品： AD7291BCPZ-RL7-ND - IC ADC I2C/SRL 22.22K 20LFCSP
AD7291BCPZ-ND - IC ADC 12BIT SAR 8CH 20-LFCSP
Data Sheet
AD7291
Rev. B | Page 17 of 28
COMMAND REGISTER (0x00)
The command register is a 16-bit write-only register that is used to set the operating modes of the AD7291. The bit functions are outlined
in Table 10. A two-byte write is necessary when writing to the command register. MSB denotes the first bit in the data stream. During
power-up, the default content of the command register is all 0s.
Table 10. Command Register Bits and Default Settings at Power-Up
MSB
LSB
Channel Bit
D15 to DB8
D7
D6
D5
D4
D3
D2
D1
D0
Function
CH0 to CH7
TSENSE
Don’t
care
Noise-delayed
bit trial and
sampling
EXT_REF
Polarity of ALERT
pin (active high/
active low)
Clear alert
RESET
Autocycle
mode
Setting
Enable = 1
Disable = 0
Enable = 1
Disable = 0
0
Enable = 1
Disable = 0
Enable = 1
Disable = 0
Active low = 1
Active high = 0
Enable = 1
Disable = 0
Enable = 1
Disable = 0
Enable = 1
Disable = 0
Table 11. Command Register Bit Function Descriptions
Bit
Mnemonic
Comment
D15 to D8
CH0 to CH7
These 8-channel address bits select the analog input channel(s) to be converted. A 1 in any of Bit D15 to
Bit D8 selects a channel for conversion. If more than one channel bit is set to 1, the AD7291 sequences
through the selected channels, starting with the lowest channel. All unused channels should be set to 0. A
channel or sequence of channels for conversion must be selected in the command register, prior to initiating
a conversion.
D7
TSENSE
This bit enables temperature conversions, which occur in the background at 5 ms intervals. The results can be
read from the TSENSE conversion result register (0x02) and the TSENSE average result register (0x03). For details,
refer to the Temperature Sensor Operation section.
D6
Don’t care
D5
Noise-
delayed bit
trial and
sampling
When this function is enabled, it delays the critical sampling intervals and bit trials when there is activity on
the I2C bus, thus ensuring improved dc performance of the AD7291. When this feature is enabled, the
conversion time may vary. This bit is disabled on power-up, and it is recommended to write a 1 to enable this
feature for normal operation.
D4
EXT_REF
Writing a Logic 1 to this bit enables the use of an external reference. The input voltage range for the external
reference is 2 V to 2.5 V. The external reference should not exceed 2.5 V or the device performance will be
adversely affected. During power-up, the default configuration has the internal reference enabled.
D3
Polarity of
ALERT pin
This bit determines the active polarity of the ALERT pin. The ALERT pin is configured for active low operation
if this bit is set to 1 and active high if this bit is set to 0. The default configuration on power-up is active high (0).
D2
Clear alert
This bit clears the content of the alert status register. Once the content of both alert status registers is cleared,
this bit should be reprogrammed to a Logic 0 to ensure that future alerts are detected.
D1
RESET
Setting this bit resets the contents of all internal registers in the AD7291 to their default states including the
command register itself. This bit is automatically returned to 0 once the reset is completed to enable the
internal registers to be reprogrammed.
D0
Autocycle
mode
Writing a 1 to this bit enables the autocycle mode of operation. In this mode, the channels selected in Bit D15
to Bit D8 are continuously converted by the AD7291. This function is used in conjunction with the limit
registers, which can be programmed to issue an alert if the conversion result exceeds the preset limit for any
channel selected for conversion.
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