參數(shù)資料
型號(hào)： EVAL-AD5934EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 8/32頁(yè)
文件大小： 0K
描述： BOARD EVALUATION FOR AD5934
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，直接數(shù)字合成（DDS）
嵌入式： 否
已用 IC / 零件： AD5934
主要屬性： 12 位數(shù)模轉(zhuǎn)換器，24 位調(diào)節(jié)字寬
次要屬性： 16MHz 2.7 V ~ 5.5 V 圖形用戶界面
已供物品： 板，線纜，軟件
產(chǎn)品目錄頁(yè)面： 797 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： AD5934YRSZ-ND - IC NTWK ANALYZER 12B 1MSP 16SSOP
AD5934YRSZ-REEL7-ND - IC CONV 12BIT 250KSPS 16SSOP
AD5934
Data Sheet
Rev. C | Page 16 of 32
2-POINT CALIBRATION
Alternatively, it is possible to minimize this error by assuming
that the frequency variation is linear and adjusting the gain
factor with a 2-point calibration. Figure 19 shows an impedance
profile based on a 2-point gain factor calculation.
101.5
98.5
54
66
05325-
086
FREQUENCY (kHz)
IM
PE
DANCE
(k
)
101.0
100.5
100.0
99.5
99.0
56
58
60
62
64
VDD = 3.3V
CALIBRATION FREQUENCY = 60kHz
TA = 25°C
MEASURED CALIBRATION IMPEDANCE = 100k
Figure 19. Impedance Profile Using a 2-Point Gain Factor Calculation
2-POINT GAIN FACTOR CALCULATION
This is an example of a 2-point gain factor calculation assuming
the following:
Output excitation voltage = 2 V p-p
Calibration impedance value, ZUNKNOWN= 100.0 k
PGA gain = ×1
Supply voltage = 3.3 V
Current-to-voltage amplifier gain resistor = 100 k
Calibration frequencies = 55 kHz and 65 kHz
Typical values of the gain factor calculated at the two calibration
frequencies read
Gain factor calculated at 55 kHz is 1.031224 × 109.
Gain factor calculated at 65 kHz is 1.035682 × 109.
Difference in gain factor (ΔGF) is
1.035682 × 109 1.031224 × 109 = 4.458000 × 1012.
Frequency span of sweep (ΔF) is 10 kHz.
Therefore, the gain factor required at 60 kHz is given by
9
-
10
1.031224
kHz
5
kHz
10
12
-
4.458000E
×
+
×
The required gain factor is 1.033453 × 109.
The impedance is calculated as previously described in the
GAIN FACTOR SETUP CONFIGURATION
When calculating the gain factor, it is important that the receive
stage is operating in its linear region. This requires careful selection
of the excitation signal range, current-to-voltage gain resistor
and PGA gain. The gain through the system shown in Figure 20
is given by
Output Excitation Voltage Range ×
UNKNOWN
Z
Resistor
Setting
Gain
× PGA Gain
05325-
089
VIN
VDD/2
RFB
ADC
LPF
ZUNKNOWN
VOUT
CURRENT-TO-VOLTAGE
GAIN SETTING RESISTOR
PGA
(×1 OR ×5)
Figure 20. System Voltage Gain
For this example, assume the following system settings:
VDD = 3.3 V
Gain setting resistor = 200 k
ZUNKNOWN = 200 k
PGA setting = ×1
The peak-to-peak voltage presented to the ADC input is 2 V p-p.
However, had the user chosen a PGA gain of ×5, the voltage
would saturate the ADC.
GAIN FACTOR RECALCULATION
The gain factor must be recalculated for a change in any of the
following parameters:
Current-to-voltage gain setting resistor
Output excitation voltage
PGA gain
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