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參數(shù)資料
型號： EVAL-AD5934EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 4/32頁
文件大小： 0K
描述： BOARD EVALUATION FOR AD5934
標(biāo)準(zhǔn)包裝： 1
主要目的： 計時，直接數(shù)字合成（DDS）
嵌入式： 否
已用 IC / 零件： AD5934
主要屬性： 12 位數(shù)模轉(zhuǎn)換器，24 位調(diào)節(jié)字寬
次要屬性： 16MHz 2.7 V ~ 5.5 V 圖形用戶界面
已供物品： 板，線纜，軟件
產(chǎn)品目錄頁面： 797 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： AD5934YRSZ-ND - IC NTWK ANALYZER 12B 1MSP 16SSOP
AD5934YRSZ-REEL7-ND - IC CONV 12BIT 250KSPS 16SSOP
AD5934
Data Sheet
Rev. C | Page 12 of 32
SYSTEM DESCRIPTION
ADC
(12 BITS)
VDD/2
DDS
CORE
(27 BITS)
DAC
Z(ω)
I2C
INTERFACE
IMAGINARY
REGISTER
REAL
REGISTER
MAC CORE
(1024 DFT)
LPF
SCL
SDA
MCLK
ROUT
VOUT
AD5934
RFB
VIN
05325-
078
PROGRAMMABLE
GAIN AMPLIFIER
×5
×1
WINDOWING
OF DATA
COS
SIN
MICROCONTROLLER
MCLK
VBIAS
Figure 14. Block Overview
The AD5934 is a high precision, impedance converter system
solution that combines an on-board frequency generator with a
12-bit, 250 kSPS ADC. The frequency generator allows an external
complex impedance to be excited with a known frequency. The
response signal from the impedance is sampled by the on-board
ADC and DFT processed by an on-board DSP engine. The DFT
algorithm returns both a real (R) and imaginary (I) data-word at
each frequency point along the sweep. The impedance magnitude
and phase is easily calculated using the following equations:
Magnitude =
2
I
R +
Phase = tan1(I/R)
To characterize an impedance profile Z(ω), generally a frequency
sweep is required such as that shown in Figure 15.
05325-
033
FREQUENCY (Hz)
IMPED
A
N
C
E
(
)
Figure 15. Impedance vs. Frequency Profile
The AD5934 permits the user to perform a frequency sweep with
a user-defined start frequency, frequency resolution, and number
of points in the sweep. In addition, the device allows the user to
program the peak-to-peak value of the output sinusoidal signal as
an excitation to the external unknown impedance connected
between the VOUT and VIN pins.
Table 5 gives the four possible output peak-to-peak voltages and
the corresponding dc bias levels for each range for 3.3 V. These
values are ratiometric with VDD. So for a 5 V supply:
p
V
3
.
3
0
.
5
98
.
1
=
×
=
1
Range
for
Voltage
Excitation
Output
p
V
24
.
2
3
.
3
0
.
5
48
.
1
=
×
=
1
Range
for
Voltage
Bias
DC
Output
Table 5. Voltage Levels Respective Bias Levels for 3.3 V
Range
No.
Output Excitation
Voltage Amplitude
Output DC Bias Level
1
1.98 V p-p
1.48 V
2
0.99 V p-p
0.74 V
3
383 mV p-p
0.31 V
4
198 mV p-p
0.179 V
The excitation signal for the transmit stage is provided on-chip
using DDS techniques that permit subhertz resolution. The receive
stage receives the input signal current from the unknown impedance,
performs signal processing, and digitizes the result. The clock for
the DDS is generated from an external reference clock that is
provided by the user at MCLK.
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