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參數資料
| 型號： | EVAL-AD5543SDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 3/20頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD5543 |
| 標準包裝： | 1 |
| DAC 的數量： | 1 |
| 位數： | 16 |
| 數據接口： | 串行 |
| 設置時間： | 500ns |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD5543 |
Data Sheet
AD5543/AD5553
Rev. F | Page 11 of 20
APPLICATIONS INFORMATION
STABILITY
VDD
VREF
VDD
U2
U1
AD5543/AD5553
VO
GND
IOUT
RFB
AD8628
C1
02917-
021
Figure 21. Optional Compensation Capacitor for Gain Peaking Prevention
In the I-to-V configuration, the IOUT of the DAC and the inverting
node of the op amp must be connected as close as possible to
each other, and proper PCB layout technique must be employed.
Because every code change corresponds to a step function, gain
peaking may occur if the op amp has limited GBP and there is
excessive parasitic capacitance at the inverting node.
An optional compensation capacitor, C1, can be added for
stability, as shown in Figure 21. C1 should be found empirically,
but 20 pF is generally adequate for the compensation.
POSITIVE VOLTAGE OUTPUT
To achieve the positive voltage output, an applied negative
reference to the input of the DAC is preferred over the output
inversion through an inverting amplifier because of the tolerance
errors of the resistors. To generate a negative reference, the
reference can be level-shifted by an op amp such that the VOUT
and GND pins of the reference become the virtual ground and
2.5 V, respectively (see Figure 22).
VREF
VDD
U2
U1
AD5543/AD5553
VO
GND
IOUT
RFB
1/2AD8628
1/2AD8620
VOUT VIN
GND
V+
V–
+5V
–5V
ADR03
+5V
–2.5V
U3
U4
C1
0V < VO < +2.5V
02917-
022
Figure 22. Positive Voltage Output Configuration
BIPOLAR OUTPUT
The AD5543/AD5553 are inherently 2-quadrant multiplying
DACs. That is, they can easily be set up for unipolar output
operation. The full-scale output polarity is the inverse of the
reference input voltage.
In some applications, it may be necessary to generate the full
4-quadrant multiplying capability or a bipolar output swing,
which is easily accomplished by using an additional U4 external
amplifier configured as a summing amplifier (see Figure 23). In
this circuit, the second amplifier, U4, provides a gain of 2 that
increases the output span magnitude to 5 V. Biasing the external
amplifier with a 2.5 V offset from the reference voltage results in a
full 4-quadrant multiplying circuit. The transfer equation of this
circuit shows that both negative and positive output voltages are
created as the input data (D) is incremented from code zero
(VOUT = 2.5 V) to midscale (VOUT = 0 V) to full-scale (VOUT =
+2.5 V).
VOUT = (D/32,768 1) × VREF (AD5543)
(3)
VOUT = (D/16,384 1) × VREF (AD5553)
(4)
For the AD5543, the resistance tolerance becomes the dominant
error of which users should be aware.
VREF
VDD
U2
U1
AD5553 ONLY
VO
GND
IOUT
RFB
1/2AD8620
VOUT VIN
GND
ADR03
U3
1/2AD8620
V+
V–
+5V
–5V
+5V
U4
C1
–2.5V < VO < +2.5V
C2
R3
R1
10k
± 0.01%
5k
± 0.01%
10k ± 0.01%
+5V
R2
02917-
023
Figure 23. 4-Quadrant Multiplying Application Circuit
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