參數(shù)資料
型號(hào)： EVAL-AD5543SDZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 2/20頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD5543
標(biāo)準(zhǔn)包裝： 1
DAC 的數(shù)量： 1
位數(shù)： 16
數(shù)據(jù)接口： 串行
設(shè)置時(shí)間： 500ns
DAC 型： 電流
工作溫度： -40°C ~ 85°C
已供物品： 板
已用 IC / 零件： AD5543
AD5543/AD5553
Data Sheet
Rev. F | Page 10 of 20
SERIAL DATA INTERFACE
The AD5543/AD5553 use a 3-wire (CS, SDI, CLK) serial data
interface. New serial data is clocked into the serial input register
in a 16-bit data-word format for the AD5543. The MSB is loaded
first. Table 5 defines the 16 data-word bits. Data is placed on the
SDI pin and clocked into the register on the positive clock edge
of CLK, subject to the data setup-and-hold time requirements
that are specified in the interface timing specifications. Only the
last 16 bits clocked into the serial register are interrogated when
the CS pin is strobed to transfer the serial register data to the DAC
register. Because most microcontrollers output serial data in 8-
bit bytes, two data bytes can be written to the AD5543/AD5553.
After loading the serial register, the rising edge of CS transfers
the serial register data to the DAC register; during this strobe,
the CLK should not be toggled. For the AD5553, with 16-bit
clock cycles, the two LSBs are ignored.
ESD PROTECTION CIRCUITS
All logic input pins contain back-biased ESD protection Zener
diodes that are connected to ground (DGND) and VDD, as
shown in Figure 20.
VDD
DIGITAL
INPUTS
DGND
5k
0
291
7-
0
20
Figure 20. Equivalent ESD Protection Circuits
PCB LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to employ compact, minimum lead length
PCB layout design. The leads to the input should be as short as
possible to minimize IR drop and stray inductance.
It is also essential to bypass the power supplies with quality
capacitors for optimum stability. Supply leads to the device
should be bypassed with 0.01 μF to 0.1 μF disc or chip ceramic
capacitors. Low ESR 1 μF to 10 μF tantalum or electrolytic
capacitors should also be applied at the supplies to minimize
transient disturbance and filter out low frequency ripple.
The PCB metal traces between VREF and RFB should also be
matched to minimize gain error.
Table 5. AD5543 Serial Input Register Data Format; Data Loaded MSB-First Format
B15 (MSB)
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0 (LSB)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Table 6. AD5553 Serial Input Register Data Format; Data Loaded MSB-First Format
B13 (MSB)1
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0 (LSB)
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1 A full 16-bit data-word can be loaded into the AD5553 serial input register, but only the last 14 bits entered are transferred to the DAC register when CS returns to
logic high.
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