
ePVP6810
VFD Controller
18 of 50
11.28.2004
(V123)
This specification is subject to change without further notice.
c) PAGE 2 (Counter3 Data Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CN37
CN36
CN35
CN34
CN33
CN32
CN31
CN30
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Bit 0 ~ Bit 7 (CN30 ~ CN37)
:
Counter3's buffer that you can read and write.
Counter3 is an 8-bit up-counter with 8-bit prescaler that allows
you to use RA PAGE2 to preset and read the counter (write
preset). After an interruption, it will reload the preset value.
7.2.12 RB (PORTB I/O Data Buffer, PORT9 Switches)
a) PAGE 0 (PORTB I/O Data Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
PB6
PB5
PB4
PB3
PB2
PB1
PB0
R-0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 0 ~ Bit 6 (PB0 ~ PB6) :
7-bit PORTB (0~6) I/O data register
You can use IOC register to define each bit as input or output.
When the PORTB is switched to ADC–
Bit 0
:
is defined as VREF
Bit 1 ~ Bit 6
:
is defined as AD1~AD6
b) PAGE 1 (PORT9, Pull High)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PH97
PH96
PH95
PH94
PH93
PH92
PH91
PH90
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Bit 0 ~ Bit 7 (PH90 ~ PH97)
:
PORT9 Bit0 ~ Bit7 pull high control register
0
disable pull high function.
1
enable pull high function
c) PAGE 2 (Counter4 Data Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CN47
CN46
CN45
CN44
CN43
CN42
CN41
CN40
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Bit 0 ~ Bit 7 (CN40 ~ CN47)
:
Counter4 buffer that you can read and write.
Counter 4 is an 8-bit up-counter with 8-bit prescaler that allows
you to use RB PAGE2 to preset and read the counter.(write
preset). After an interruption, it will reload the preset value.