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參數(shù)資料
| 型號： | EPVP6810 |
| 廠商： | ELAN Microelctronics Corp . |
| 英文描述： | VFD Controller |
| 中文描述： | 變頻控制器 |
| 文件頁數(shù)： | 34/50頁 |
| 文件大?。?/td> | 343K |
| 代理商： | EPVP6810 |
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ePVP6810
VFD Controller
28 of 50
11.28.2004
(V123)
This specification is subject to change without further notice.
COUNTER3 time out
IOCD bit0=1
And "ENI"
1) Wake-up
2) Interrupt (jump to Address 8 on
Page0)
3) After RETI instruction, jump to
SLEP Next instruction
Interrupt
(jump to Address 8
on Page0)
Interrupt
(jump to Address 8
on Page0)
COUNTER4 time out
IOCD bit1=1
And "ENI"
1) Wake-up
2) Interrupt (jump to Address 8 on
Page0)
3) After RETI instruction, jump to
SLEP Next instruction
Interrupt
(jump to Address 8
on Page0)
Interrupt
(jump to Address 8
on Page0)
COUNTER5 time out
IOCD bit2=1
And "ENI"
1) Wake-up
2) Interrupt (jump to Address 8 on
Page0)
3) After RETI instruction, jump to
SLEP Next instruction
Interrupt
(jump to Address 8
on Page0)
Interrupt
(jump to Address 8
on Page0)
INT1~4
IOCF bit4=1 or IOCF
bit5=1 IOCF bit6 = 1
or IOCF bit7= 1
And “ENI
1) Wake-up
2)Interrupt (jump to Address 8 on
Page0)
3) after RETI instruction, jump to
SLEP Next instruction
Interrupt
(jump to Address 8
on Page0)
Interrupt
(jump to Address 8
on Page0)
IR
IOCF bit3= 1
And “ENI
1) Wake-up
2) Interrupt (jump to Address 8 on
Page0)
3) After RETI instruction, jump to
SLEP Next instruction
Interrupt
(jump to Address 8
on Page0)
Interrupt
(jump to Address 8
on Page0)
ADI
IOCE bit5 = 1
And “ENI
No function
Interrupt
(jump to Address 8
on Page0)
Interrupt
(jump to Address 8
on Page0)
NOTES:
1.
PORT90 interrupt function is controlled by IOCF Bit 3. It is a falling edge or rising edge
trigger (controlled by CONT register Bit7).
2. PORT9 (1~4) interrupt functions are controlled by IOCF Bits 4, 5, 6, & 7). They are falling
edge triggers.
7.4 Application notes
1
Call-table instruction:
Because the call-table instruction can only change the Program Counter's bit7 ~ bit0 at
each time, only 256 addresses can be searched once.
But each program page contains 1024 addresses, if call each 256 addresses as a zone,
Then each page constitutes by four zones.
When a table overlaps two zones, a bug would occur during address searching.
So the member of program must examine the .LST file at any time, the .LST file will jot
down the information that Assembler generated, for example source code, the coding of
instruction , instruction address, error message etc.
2
Operation requirement for the CPU
The system frequency must adds a latency time ( 14.33 MHz about 250 ms
about 450 ms.). After RA register was setting, it will offer the stable system frequency for
the operation.
17.91 MHz
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