參數(shù)資料
型號(hào): EPVP6810
廠商: ELAN Microelctronics Corp .
英文描述: VFD Controller
中文描述: 變頻控制器
文件頁數(shù): 19/50頁
文件大?。?/td> 343K
代理商: EPVP6810
ePVP6810
VFD Controller
This specification is subject to change without further notice.
11.28.2004 (V1.23)
13 of 50
For PLL Clock = 447.829kHz (CLK2~CLK0 = 000)
ADCLK1
ADCLK0
Sampling rate
Operation voltage
0
0
37.4K
>=3.0V
0
1
18.7K
>=3.0V
1
0
9.3K
>=2.5V
1
1
4.7K
>=2.5V
This is a CMOS multi-channel 10-bit successive approximation A/D converter.
Features
:
74.6kHz maximum conversion speed at 5V
Adjusted full scale input
External reference voltage input or internal (VDD) reference voltage
6 analog inputs multiplexed into one A/D converter
Power down mode for power saving
A/D conversion complete interrupt
Interrupt register, A/D control and status register, and A/D data register
Fig. 4 ADC Voltage Control Logic
fadcon = fadc / 12
fpll
Mx
fs
Nx = 1
Nx = 2
Nx = 4
Nx = 8
14.331MHz
16
895.658kHz
74.638kHz
37.391kHz
18.659khz
9.329kHz
10.747MHz
12
895.658kHz
74.638kHz
37.391kHz
18.659khz
9.329kHz
7.165MHz
8
895.658kHz
74.638kHz
37.391kHz
18.659khz
9.329kHz
3.582MHz
4
895.658kHz
74.638kHz
37.391kHz
18.659khz
9.329kHz
1.791MHz
2
895.658kHz
74.638kHz
37.391kHz
18.659khz
9.329kHz
895.658kHz
1
895.658kHz
74.638kHz
37.391kHz
18.659khz
9.329kHz
447.829kHz
1
447.829kHz
37.391kHz
18.659khz
9.329kHz
4.665kHz
Bit 5 ~ Bit 7 (IN0 ~ IN2)
:
Input channel selection of AD converter
Programmable
divider
1/Mx
Divider
Nx
10-bit
ADC
ADCLK1~ADCLK0
fs
ADC output
PLL
ENPLL
CLK2 ~ CLK0
fpll
fad
c
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