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| 型號(hào)： | EPF10K100B |
| 英文描述： | Programmable Logic |
| 中文描述： | 可編程邏輯 |
| 文件頁(yè)數(shù)： | 22/138頁(yè) |
| 文件大?。?/td> | 2116K |
| 代理商： | EPF10K100B |
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118
Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
Table 114 summarizes the ClockLock and ClockBoost parameters.
Notes:
(1)
To implement the ClockLock and ClockBoost circuitry with the MAX+PLUS II software, designers must specify the
input frequency. The MAX+PLUS II software tunes the PLL in the ClockLock and ClockBoost circuitry to this
frequency. The fCLKDEV parameter specifies how much the incoming clock can differ from the specified frequency
during device operation. Simulation does not reflect this parameter.
(2)
During device configuration, the ClockLock and ClockBoost circuitry is configured before the rest of the device. If
the incoming clock is supplied during configuration, the ClockLock and ClockBoost circuitry locks during
configuration, because the tLOCK value is less than the time required for configuration.
(3)
The tJITTER specification is measured under long-term observation.
Power
Consumption
The supply power (P) for FLEX 10K devices can be calculated with the
following equation:
P = PINT + PIO = (ICCSTANDBY + ICCACTIVE) × VCC + PIO
Typical ICCSTANDBY values are shown as ICC0 in the FLEX 10K 5.0-V
sheet. The ICCACTIVE value depends on the switching frequency and the
application logic. This value is calculated based on the amount of current
that each LE typically consumes. The PIO value, which depends on the
device output load characteristics and switching frequency, can be
calculated using the guidelines given in Application Note 74 (Evaluating
Table 114. ClockLock & ClockBoost Parameters
Symbol
Parameter
Min
Typ
Max
Unit
tR
Input rise time
2
ns
tF
Input fall time
2
ns
tINDUTY
Input duty cycle
45
55
%
fCLK1
Input clock frequency (ClockBoost clock multiplication factor equals 1)
30
80
MHz
tCLK1
Input clock period (ClockBoost clock multiplication factor equals 1)
12.5
33.3
ns
fCLK2
Input clock frequency (ClockBoost clock multiplication factor equals 2)
16
50
MHz
tCLK2
Input clock period (ClockBoost clock multiplication factor equals 2)
20
62.5
ns
fCLKDEV1 Input deviation from user specification in MAX+PLUS II (ClockBoost clock
multiplication factor equals 1)
±1
MHz
fCLKDEV2 Input deviation from user specification in MAX+PLUS II (ClockBoost clock
multiplication factor equals 2)
±0.5
MHz
tINCLKSTB Input clock stability (measured between adjacent clocks)
100
ps
tLOCK
Time required for ClockLock or ClockBoost to acquire lock
10
s
tJITTER
Jitter on ClockLock or ClockBoost-generated clock
1
ns
tOUTDUTY Duty cycle for ClockLock or ClockBoost-generated clock
40
50
60
%
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相關(guān)代理商/技術(shù)參數(shù) |
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| EPF10K100BFC256-1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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| EPF10K100BFC256-2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EPF10K100BFC256-2DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| EPF10K100BFC256-3DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
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