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鍙冩暩璩囨枡
鍨嬭櫉锛� EP2S90F1508C3N
寤犲晢锛� Altera
鏂囦欢闋佹暩锛� 95/768闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC STRATIX II FPGA 90K 1508-FBGA
鐢㈠搧鍩硅〒妯″锛� Three Reasons to Use FPGA's in Industrial Designs
妯欐簴鍖呰锛� 7
绯诲垪锛� Stratix® II
LAB/CLB鏁革細 4548
閭忚集鍏冧欢/鍠厓鏁革細 90960
RAM 浣嶇附瑷堬細 4520488
杓稿叆/杓稿嚭鏁革細 902
闆绘簮闆诲锛� 1.15 V ~ 1.25 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 85°C
灏佽/澶栨锛� 1508-BBGA
渚涙噳鍟嗚ō鍌欏皝瑁濓細 1508-FBGA锛�30x30锛�
鍏跺畠鍚嶇ū锛� 544-1921
EP2S90F1508C3N-ND
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730闋�绗�731闋�绗�732闋�绗�733闋�绗�734闋�绗�735闋�绗�736闋�绗�737闋�绗�738闋�绗�739闋�绗�740闋�绗�741闋�绗�742闋�绗�743闋�绗�744闋�绗�745闋�绗�746闋�绗�747闋�绗�748闋�绗�749闋�绗�750闋�绗�751闋�绗�752闋�绗�753闋�绗�754闋�绗�755闋�绗�756闋�绗�757闋�绗�758闋�绗�759闋�绗�760闋�绗�761闋�绗�762闋�绗�763闋�绗�764闋�绗�765闋�绗�766闋�绗�767闋�绗�768闋�
5鈥�38
Altera Corporation
Stratix II Device Handbook, Volume 1
April 2011
Timing Model
tM512 DATACO1
Clock-to-output delay
when using output
registers
298
478
298
501
284
298
548
298
640
ps
tM512 DATACO2
Clock-to-output delay
without output registers
2,102
2,345
2,102
2,461
2,003
2,102
2,695
2,102
3,141
ps
tM512 CL KL
Minimum clock low time
1,315
1,380
1,512
1,762
ps
tM512 CL KH
Minimum clock high time 1,315
1,380
1,512
1,762
ps
tM512 CL R
Minimum clear pulse
width
144
151
165
192
ps
Notes to Table 5鈥�40:
(1)
FMAX of M512 block obtained using the Quartus II software does not necessarily equal to 1/TM512RC.
(2)
These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
(3)
These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
(4)
For the -3 and -5 speed grades, the minimum timing is for the commercial temperature grade. Only -4 speed grade
devices offer the industrial temperature grade.
(5)
For the -4 speed grade, the first number is the minimum timing parameter for industrial devices. The second
number is the minimum timing parameter for commercial devices.
Table 5鈥�41. M4K Block Internal Timing Microparameters (Part 1 of 2)
Symbol
Parameter
-3 Speed
Grade (2)
-3 Speed
Grade (3)
-4 Speed
Grade
-5 Speed
Grade
Unit
Min
Max
Min
Max
Min
Max
Min
Max
tM4KRC
Synchronous read cycle
time
1,462
2,240
1,462
2,351
1,393
1,462
2,575
1,462
3,000
ps
tM4KWERESU
Write or read enable
setup time before clock
22
23
25
29
ps
tM4KWEREH
Write or read enable
hold time after clock
203
213
233
272
ps
tM4KBESU
Byte enable setup time
before clock
22
23
25
29
ps
tM4KBEH
Byte enable hold time
after clock
203
213
233
272
ps
Table 5鈥�40. M512 Block Internal Timing Microparameters (Part 2 of 2)
Note (1)
Symbol
Parameter
-3 Speed
Grade (2)
-3 Speed
Grade (3)
-4 Speed
Grade
-5 Speed
Grade
Unit
Min
(4)
Max
Min
(4)
Max
Min
(5)
Max
Min
(4)
Max
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