5–96
Altera Corporation
Stratix II Device Handbook, Volume 1
April 2011
JTAG Timing Specifications
JTAG Timing
Specifications
Figure 5–10 shows the timing requirements for the JTAG signals.
Figure 5–10. Stratix II JTAG Waveforms
Table 5–100. DQS Phase Offset Delay Per Stage
Speed Grade
Min
Max
Unit
-3
9
14
ps
-4
9
14
ps
-5
9
15
ps
(1)
The delay settings are linear.
(2)
The valid settings for phase offset are -64 to +63 for frequency mode 0 and -32 to
+31 for frequency modes 1, 2, and 3.
(3)
The typical value equals the average of the minimum and maximum values.
Table 5–101. DDIO Outputs Half-Period Jitter
Name
Description
Max
Unit
tOUTHAL FJITTER
Half-period jitter (PLL driving DDIO outputs)
200
ps
(1)
The worst-case half period is equal to the ideal half period subtracted by the DCD
and half-period jitter values.
(2)
The half-period jitter was characterized using a PLL driving DDIO outputs.
TDO
TCK
tJPZX
t
JPCO
tJPH
t JPXZ
tJCP
tJPSU
t JCL
tJCH
TDI
TMS