
Altera Corporation
5–7
January 2008
Stratix II Device Handbook, Volume 2
High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices
other phase shifts in 45° increments. These settings are made statically in
the Quartus II MegaWizard software. Figure 5–4 shows the transmitter in clock output mode.
Figure 5–4. Transmitter in Clock Output Mode
The serializer can be bypassed to support DDR (2) and SDR (1)
operations. The I/O element (IOE) contains two data output registers that
each can operate in either DDR or SDR mode. The clock source for the
registers in the IOE can come from any routing resource, from the fast
PLL, or from the enhanced PLL.
Figure 5–5 shows the bypass path.
Figure 5–5. Serializer Bypass
Transmitter Circuit
diffioclk
load_en
Parallel
Series
Internal
Logic
tx_outclock
IOE
Serializer
Internal Logic
IOE Supports SDR, DDR, or
Non-Registered Data Path
Not used (connection exists)
tx_out