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- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗4351 > EP2S60F672C5 (Altera)IC STRATIX II FPGA 60K 672-FBGA PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛�
EP2S60F672C5
寤犲晢锛�
Altera
鏂囦欢闋佹暩(sh霉)锛�
195/768闋�
鏂囦欢澶у皬锛�
0K
鎻忚堪锛�
IC STRATIX II FPGA 60K 672-FBGA
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛�
Three Reasons to Use FPGA's in Industrial Designs
妯�(bi膩o)婧�(zh菙n)鍖呰锛�
10
绯诲垪锛�
Stratix® II
LAB/CLB鏁�(sh霉)锛�
3022
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛�
60440
RAM 浣嶇附瑷堬細
2544192
杓稿叆/杓稿嚭鏁�(sh霉)锛�
492
闆绘簮闆诲锛�
1.15 V ~ 1.25 V
瀹夎椤炲瀷锛�
琛ㄩ潰璨艰
宸ヤ綔婧害锛�
0°C ~ 85°C
灏佽/澶栨锛�
672-BBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細
672-BGA锛�27x27锛�
閰嶇敤锛�
544-1700-ND - DSP KIT W/STRATIX II EP2S60N
544-1697-ND - NIOS II KIT W/STRATIX II EP2S60N
鍏跺畠鍚嶇ū锛�
544-1128
EP2S60F672C5ES
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1鈥�10Altera CorporationStratix II Device Handbook, Volume 2July 2009Enhanced PLLsFigure 1鈥�6. Enhanced PLL PortsNotes to Figure 1鈥�6:(1)Enhanced and fast PLLs share this input pin.(2)These are either single-ended or differential pins.(3)The primary and secondary clock input can be fed from any one of four clock pins located on the same side of thedevice as the PLL.(4)Can drive to the global or regional clock networks or the dedicated external clock output pins.(5)These dedicated output clocks are fed by the C[5..0] counters.Tables 1鈥�4 and 1鈥�5 describe all the enhanced PLL ports.clkswitchscandatascanclkpllenaC[5..0]lockedPhysical PinclklossaresetpfdenaSignal Driven by Internal LogicSignal Driven to Internal LogicInternal Clock Signalscandonepll_out0pscandataoutfbinclkbad[1..0](1)(2), (3)pll_out0npll_out1ppll_out1npll_out2ppll_out2n(5)scanwritescanread(5)activeclockinclk0inclk1(4)(2), (3)Table 1鈥�4. Enhanced PLL Input Signals (Part 1 of 2)PortDescriptionSourceDestinationinclk0Primary clock input to the PLL.Pin or another PLLn counterinclk1Secondary clock input to the PLL.Pin or another PLLn counterfbinExternal feedback input to the PLL.PinPFDpllenaEnable pin for enabling or disablingall or a set of PLLs. Active high.PinGeneral PLL controlsignalclkswitchSwitch-over signal used to initiateexternal clock switch-over control.Active high.Logic arrayPLL switch-over circuit
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- 鎼滅储
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