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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� EP2S60F672C5
寤犲晢锛� Altera
鏂囦欢闋佹暩(sh霉)锛� 185/768闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC STRATIX II FPGA 60K 672-FBGA
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Three Reasons to Use FPGA's in Industrial Designs
妯�(bi膩o)婧栧寘瑁濓細 10
绯诲垪锛� Stratix® II
LAB/CLB鏁�(sh霉)锛� 3022
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 60440
RAM 浣嶇附瑷堬細 2544192
杓稿叆/杓稿嚭鏁�(sh霉)锛� 492
闆绘簮闆诲锛� 1.15 V ~ 1.25 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 85°C
灏佽/澶栨锛� 672-BBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 672-BGA锛�27x27锛�
閰嶇敤锛� 544-1700-ND - DSP KIT W/STRATIX II EP2S60N
544-1697-ND - NIOS II KIT W/STRATIX II EP2S60N
鍏跺畠鍚嶇ū锛� 544-1128
EP2S60F672C5ES
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Altera Corporation
1鈥�1
July 2009
1. PLLs in Stratix II and
Stratix II GX Devices
Introduction
Stratix II and Stratix II GX device phase-locked loops (PLLs) provide
robust clock management and synthesis for device clock management,
external system clock management, and high-speed I/O interfaces.
Stratix II devices have up to 12 PLLs, and Stratix II GX devices have up to
8 PLLs. Stratix II and Stratix II GX PLLs are highly versatile and can be
used as a zero delay buffer, a jitter attenuator, low skew fan out buffer, or
a frequency synthesizer.
Stratix II and Stratix II GX devices feature both enhanced PLLs and fast
PLLs. Stratix II and Stratix II GX devices have up to four enhanced PLLs.
Stratix II devices have up to eight fast PLLs and Stratix II GX devices have
up to four PLLs. Both enhanced and fast PLLs are feature rich, supporting
advanced capabilities such as clock switchover, reconfigurable phase
shift, PLL reconfiguration, and reconfigurable bandwidth. PLLs can be
used for general-purpose clock management, supporting multiplication,
phase shifting, and programmable duty cycle. In addition, enhanced
PLLs support external clock feedback mode, spread-spectrum clocking,
and counter cascading. Fast PLLs offer high speed outputs to manage the
high-speed differential I/O interfaces.
Stratix II and Stratix II GX devices also support a power-down mode
where clock networks that are not being used can easily be turned off,
reducing the overall power consumption of the device. In addition,
Stratix II and Stratix II GX PLLs support dynamic selection of the PLL
input clock from up to five possible sources, giving you the flexibility to
choose from multiple (up to four) clock sources to feed the primary and
secondary clock input ports.
The Altera Quartus II software enables the PLLs and their features
without requiring any external devices.
SII52001-4.6
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
24AA01HT-I/OT IC EEPROM 1KBIT 400KHZ SOT23-5
24LC01BT/OT IC EEPROM 1KBIT 400KHZ SOT23-5
24C00T/OT IC EEPROM 128BIT 400KHZ SOT23-5
445730-3 CONN D-SUB RCPT HSING 8C8 MIX
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EP2S60F672I4N 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix II 3022 LABs 492 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP2S90 鍒堕€犲晢:ALTERA 鍒堕€犲晢鍏ㄧū:Altera Corporation 鍔熻兘鎻忚堪:1. Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet
EP2S90F1020C3 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix II 4548 LABs 758 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256