參數(shù)資料
型號： EP20K60ETI144-2ES
英文描述： FPGA
中文描述： FPGA的
文件頁數(shù)： 16/114頁
文件大小： 1623K
代理商： EP20K60ETI144-2ES
112
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Power
Consumption
To estimate device power consumption, use the interactive power
estimator on the Altera web site at http://www.altera.com.
Configuration &
Operation
The APEX 20K architecture supports several configuration schemes.
This section summarizes the device operating modes and available
device configuration schemes.
Operating Modes
The APEX architecture uses SRAM configuration elements that
require configuration data to be loaded each time the circuit powers
up. The process of physically loading the SRAM data into the device
is called configuration. During initialization, which occurs
immediately after configuration, the device resets registers, enables
I/O pins, and begins to operate as a logic device. The I/O pins are
tri-stated during power-up, and before and during configuration.
Together, the configuration and initialization processes are called
command mode; normal device operation is called user mode.
Before and during device configuration, all I/O pins are pulled to
VCCIO by a built-in weak pull-up resistor.
Table 114. Selectable I/O Standard Output Delays
Symbol
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
Min
LVCMOS
0.00
ns
LVTTL
0.00
ns
2.5 V
0.00
0.09
0.10
ns
1.8 V
2.49
2.98
3.03
ns
PCI
–0.03
0.17
0.16
ns
GTL+
0.75
0.76
ns
SSTL-3 Class I
1.39
1.51
1.50
ns
SSTL-3 Class II
1.11
1.23
ns
SSTL-2 Class I
1.35
1.48
1.47
ns
SSTL-2 Class II
1.00
1.12
ns
LVDS
–0.48
ns
CTT
0.00
ns
AGP
0.00
ns
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