參數(shù)資料
型號(hào)： EP1K50FI484-2DX
英文描述： Field Programmable Gate Array (FPGA)
中文描述： 現(xiàn)場(chǎng)可編程門陣列（FPGA）
文件頁(yè)數(shù)： 55/86頁(yè)
文件大?。?/td> 1263K
代理商： EP1K50FI484-2DX
Altera Corporation
59
ACEX 1K Programmable Logic Device Family Data Sheet
Development
13
Tools
Tables 27 through 29 describe the ACEX 1K external timing parameters
and their symbols.
Notes to tables:
(1)
External reference timing parameters are factory-tested, worst-case values specified by Altera. A representative
subset of signal paths is tested to approximate typical device applications.
(2)
Contact Altera Applications for test circuit specifications and test conditions.
(3)
These timing parameters are sample-tested only.
(4)
This parameter is measured with the measurement and test conditions, including load, specified in the PCI Local
Bus Specification, Revision 2.2.
Table 27. External Reference Timing Parameters
Symbol
Parameter
Conditions
tDRR
Register-to-register delay via four LEs, three row interconnects, and four local
interconnects
Table 28. External Timing Parameters
Symbol
Parameter
Conditions
tINSU
Setup time with global clock at IOE register
tINH
Hold time with global clock at IOE register
tOUTCO
Clock-to-output delay with global clock at IOE register
tPCISU
Setup time with global clock for registers used in PCI designs
tPCIH
Hold time with global clock for registers used in PCI designs
tPCICO
Clock-to-output delay with global clock for registers used in PCI designs
Table 29. External Bidirectional Timing Parameters
Symbol
Parameter
Conditions
tINSUBIDIR
Setup time for bidirectional pins with global clock at same-row or same-
column LE register
tINHBIDIR
Hold time for bidirectional pins with global clock at same-row or same-column
LE register
tOUTCOBIDIR
Clock-to-output delay for bidirectional pins with global clock at IOE register
CI = 35 pF
tXZBIDIR
Synchronous IOE output buffer disable delay
CI = 35 pF
tZXBIDIR
Synchronous IOE output buffer enable delay, slow slew rate = off
CI = 35 pF
相關(guān)PDF資料
PDF描述
EP1K50FI484-2F Field Programmable Gate Array (FPGA)
EP1K50FI484-2P Field Programmable Gate Array (FPGA)
EP1K50FI484-2X Field Programmable Gate Array (FPGA)
EP1K50FI484-3F Field Programmable Gate Array (FPGA)
EP1K50QC208-1DX Field Programmable Gate Array (FPGA)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP1K50FI484-2F 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EP1K50FI484-2P 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EP1K50FI484-2X 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EP1K50FI484-3F 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EP1K50QC2081 制造商:ALTERA 功能描述:*
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*