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參數(shù)資料
| 型號： | EP1K50FI484-2DX |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | 現(xiàn)場可編程門陣列（FPGA） |
| 文件頁數(shù)： | 30/86頁 |
| 文件大?。?/td> | 1263K |
| 代理商： | EP1K50FI484-2DX |
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36
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
f For more information, search for “SameFrame” in MAX+PLUS II Help.
Note:
(1)
This option is supported with a 256-pin FineLine BGA package and SameFrame
migration.
ClockLock &
ClockBoost
Features
To support high-speed designs, -1 and -2 speed grade ACEX 1K devices
offer ClockLock and ClockBoost circuitry containing a phase-locked loop
(PLL) that is used to increase design speed and reduce resource usage.
The ClockLock circuitry uses a synchronizing PLL that reduces the clock
delay and skew within a device. This reduction minimizes clock-to-
output and setup times while maintaining zero hold times. The
ClockBoost circuitry, which provides a clock multiplier, allows the
designer to enhance device area efficiency by sharing resources within the
device. The ClockBoost feature allows the designer to distribute a low-
speed clock and multiply that clock on-device. Combined, the ClockLock
and ClockBoost features provide significant improvements in system
performance and bandwidth.
The ClockLock and ClockBoost features in ACEX 1K devices are enabled
through the Altera software. External devices are not required to use these
features. The output of the ClockLock and ClockBoost circuits is not
available at any of the device pins.
The ClockLock and ClockBoost circuitry lock onto the rising edge of the
incoming clock. The circuit output can drive the clock inputs of registers
only; the generated clock cannot be gated or inverted.
The dedicated clock pin (GCLK1) supplies the clock to the ClockLock and
ClockBoost circuitry. When the dedicated clock pin is driving the
ClockLock or ClockBoost circuitry, it cannot drive elsewhere in the
device.
Table 10. ACEX 1K SameFrame Pin-Out Support
Device
256-Pin
FineLine
BGA
484-Pin
FineLine
BGA
EP1K10
v
EP1K30
v
EP1K50
vv
EP1K100
vv
相關PDF資料 |
PDF描述 |
|---|---|
| EP1K50FI484-2F | Field Programmable Gate Array (FPGA) |
| EP1K50FI484-2P | Field Programmable Gate Array (FPGA) |
| EP1K50FI484-2X | Field Programmable Gate Array (FPGA) |
| EP1K50FI484-3F | Field Programmable Gate Array (FPGA) |
| EP1K50QC208-1DX | Field Programmable Gate Array (FPGA) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EP1K50FI484-2F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50FI484-2P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50FI484-2X | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50FI484-3F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50QC2081 | 制造商:ALTERA 功能描述:* |
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