參數(shù)資料
型號(hào)： EM6617VVVST11A
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 0.032768 MHz, RISC MICROCONTROLLER
封裝： STICKY TAPE
文件頁(yè)數(shù)： 8/66頁(yè)
文件大?。?/td> 759K
代理商： EM6617VVVST11A
EM6617-1
EM Microelectronic-Marin SA , 3/99 Rev. B/258
8
5. Reset
Figure 8. illustrates the reset structure of the EM6617-1. There are six possible reset sources :
(1) Internal initial reset from the Power On Reset (POR) circuitry.
(2) External reset from the Reset terminal.
(3) External reset by simultaneous high/low inputs to port A.
(Combinations are defined in the registers
OptInpRSel1
and
OptInpRSel2)
(4) Internal reset from the Digital Watchdog.
(5) Internal reset from the Oscillation Detection Circuit.
(6) Internal reset when sleep mode is activated.
--> POR
--> System Reset, Reset CPU
--> System Reset, Reset CPU
--> System Reset, Reset CPU
--> System Reset, Reset CPU
--> System Reset, Reset CPU
All reset sources activate the System Reset and the Reset CPU
. The ‘System Reset Delay’ ensures that the
system reset remains active long enough for all system functions to be reset (active for n system clock cycles).
The ‘CPU Reset Delay’ ensures that the reset CPU remains active until the oscillator is in stable oscillation.
As well as activating the system reset and the reset CPU, the POR also resets all option registers and the sleep
enable (
SleepEn)
latch. System reset and reset CPU do not reset the option registers nor the
SleepEn
latch.
Reset state can be shown on Strobe terminal by selecting
StrobeOutSel1,0 = 0
in
OPTCandStr
register.
Figure 8. Reset Structure
S ystem R eset
D elay
C PU R eset
D elay
E nable
A ctivate
D igital
W atchdog
O scillation
D etection
R eset from P ort A
Input C om bination
R eset P AD
Sleep
O ptInpR Sleep
R eset
C P U
Inhibit
O scillation
D etection
Inhibit
D igital
W atchdog
PO R
PO R to O ption
R egisters & SleepEn
Latch
D EBO U N C E
Sleep
Latch
S leepE n
Latch
PO R
Internal D ata Bus
W rite R eset
R ead Status
W rite Active
R ead Status
C k[10]
C k[1]
C k[8]
C k[1]
C k[15]
PO R
Analogue
Filter
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