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參數(shù)資料
| 型號： | EM6617VVVST11A |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 0.032768 MHz, RISC MICROCONTROLLER |
| 封裝： | STICKY TAPE |
| 文件頁數(shù)： | 24/66頁 |
| 文件大?。?/td> | 759K |
| 代理商： | EM6617VVVST11A |
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EM6617-1
EM Microelectronic-Marin SA , 3/99 Rev. B/258
24
8.2 Frequency Select and Up/Down Counting
8 different input clocks can be selected to drive the Counter. The selection is done with bits
CountFSel2…0
in
register
RegCCntl1
. 6 of this input clocks are coming from the prescaler. The maximum prescaler clock
frequency for the counter is half the system clock and the lowest is 1Hz. Therefore a complete counter roll over
can take as much as 17.07 minutes (1Hz clock, 10 bit length) or as little as 977
μ
s (Ck[15], 4 bit length). The
IRQCount0
, generated at each roll over, can be used for time bases, measurements length definitions, input
polling, wake up from Halt mode, etc. The
IRQCount0
and
IRQComp
are generated with the system clock
Ck[16] rising edge. IRQCount0 condition in up count mode is : reaching 3FF if 10-bit counter length (or FF, 3F,
F in 8, 6, 4-bit counter length). In down count mode the condition is reaching ‘0’. The non-selected bits are ‘don’t
care’. For IRQComp refer to section 8.4.
Note: The Prescaler and the Microprocessor clock’s are usually non-synchronous, therefore time bases
generated are max. n, min. n-1 clock cycles long (n being the selected counter start value in count down mode).
However the prescaler clock can be synchronized with μP commands using for instance the prescaler reset
function.
Figure 18. Counter Clock Timing
Prescaler Frequencies or Debounced Port A Clocks
The two remaining clock sources are coming from the PA[0] or PA[3] terminals. Refer to the Figure 12 on page
14 for details. Both sources can be either debounced (Ck[11] or Ck[8]) or direct inputs, the input polarity can
also be chosen. The output after the debouncer polarity selector is named PA3 , PA0 respectively. For the
debouncer and input polarity selection refer to chapter 7.2.4.
In the case of port A input clock without debouncer, the counting clock frequency will be half the input clock on
port A. The counter advances on every odd numbered port A negative edge ( divided clock is high level ).
IRQCount0 and IRQComp will be generated on the rising PA3 or PA0 input clock edge. In this condition the
EM6617-1 is able to count with a higher clock rate as the internal system clock (Hi-Frequency Input). Maximum
port A input frequency is limited to 200kHz. If higher frequencies are needed, please contact EM-Marin.
In both, up or down count (default) mode, the counter is cyclic. The counting direction is chosen in register
RegCCntl1
bit
Up/Down
(default ‘0’ is down count). The counter increases or decreases its value with each
positive clock edge of the selected input clock source. Start up synchronization is necessary because one can
not always know the clock status when enabling the counter. With EvCount=0, the counter will only start on the
next positive clock edge after a previously latched negative edge, while the
Start
bit was already set to ‘1’. This
synchronization is done differently if event count mode (bit
EvCount
) is chosen. Refer also to Figure 19.
Internal Clock Synchronization.
Non-D ebounced Port A Clocks (System Clock Independent)
System C lock
Prescaler Clock
Counting
Counter IRQ ’s
Divided C lock
System C lock
Port A Clock
Counting
Counter IRQ ’s
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