參數(shù)資料
型號(hào)： EM6617VVVST11A
元件分類(lèi)： 微控制器/微處理器
英文描述： 4-BIT, MROM, 0.032768 MHz, RISC MICROCONTROLLER
封裝： STICKY TAPE
文件頁(yè)數(shù)： 19/66頁(yè)
文件大?。?/td> 759K
代理商： EM6617VVVST11A
EM6617-1
EM Microlectronic-Marin SA , 3/99 Rev. B/258
19
7.4.4 PWM and Frequency Output
PB[3] can also be used to output the PWM (Pulse Width Modulation) signal from the 10-Bit Counter, the
Ck[11], Ck[16] as well as the Ck[12] prescaler frequencies.
-Selecting PWM output on PB[3] with bit
PWMOn
in register
RegPresc
and running the counter.
-Selecting Ck[11] output on PB[2] with bit
PB1kHzOut
in register
OPTFSelPB
-Selecting Ck[16] output on PB[1] with bit
PB32kHzOut
in register
OPTFSelPB
-Selecting Ck[12 ] output on PB[0] with bit
PB2kHzOut
in register
OPTFSelPB
7.5 Port B registers
Table 7.5.1 Register RegPBData
Bit
3
2
1
0
R* : Direct read on pin (not the internal register read).
Name
PBData[3]
PBData[2]
PBData[1]
PBData[0]
Reset
-
-
-
-
R/W
R/W*
R/W*
R/W*
R/W*
Description
PB[3] input and output
PB[2] input and output
PB[1] input and output
PB[0] input and output
Table 7.5.2 Register RegPBCntl
Bit
3
2
1
0
Default "0" is: Port B in input mode
Name
PBIOCntl[3]
PBIOCntl[2]
PBIOCntl[1]
PBIOCntl[0]
Reset
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
I/O control for PB[3]
I/O control for PB[2]
I/O control for PB[1]
I/O control for PB[0]
Table 7.5.3 Register OPTFSelPB
Bit
Name
power on
value
0
0
0
0
R/W
Description
3
2
1
0
PB1kHzOut
PB32kHzOut
PB2kHzOut
InpResSleep
R/W
R/W
R/W
R/W
ck[11] output on PB[2]
ck[16] output on PB[1]
ck[12] output on PB[0]
Reset From SLEEP with Port A
Default "0" is: No frequency output, port A Input reset can not reset the SLEEP mode.
Table 7.5.4 Option Register OPTNoPdPB
Bit
Name
power on
value
0
0
0
0
R/W
Description
3
2
1
0
NoPdPB[3]
NoPdPB[2]
NoPdPB[1]
NoPdPB[0]
R/W
R/W
R/W
R/W
No pull-down on PB[3]
No pull-down on PB[2]
No pull-down on PB[1]
No pull-down on PB[0]
Default "0" is: Pull-down on
Table 7.5.5 Option Register OPTNchOpDPB
Bit
Name
power on
value
0
0
0
0
R/W
Description
3
2
1
0
NchOpDPB[3]
NchOpDPB[2]
NchOpDPB[1]
NchOpDPB[0]
R/W
R/W
R/W
R/W
N-Channel Open Drain on PB[3]
N-Channel Open Drain on PB[2]
N-Channel Open Drain on PB[1]
N-Channel Open Drain on PB[0]
Default "0" is: CMOS on PB[3..0]
7.6 Port C
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