參數(shù)資料
型號(hào)： EM6617VVVST11A
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 0.032768 MHz, RISC MICROCONTROLLER
封裝： STICKY TAPE
文件頁(yè)數(shù)： 6/66頁(yè)
文件大?。?/td> 759K
代理商： EM6617VVVST11A
EM6617-1
EM Microelectronic-Marin SA , 3/99 Rev. B/258
6
3. Operating Modes
The EM6617-1 has two low power dissipation modes, standby and sleep. Figure 5 is a transition diagram for
these modes.
3.1 Active Mode
The active mode is the actual CPU running mode. Instructions are read from the internal ROM and executed by
the CPU. Leaving active mode via the halt instruction to go into standby mode, the
Sleep
bit write to go into
Sleep mode or a reset from port A to go into reset mode.
3.2 Standby Mode
Executing a halt instruction puts the
EM6617-1 into standby mode. The voltage
regulator, oscillator, watchdog timer, ADC,
interrupts, SWB, timers and counters are
operating. However, the CPU stops since the
clock related to instruction execution stops.
Registers, RAM and I/O pins retain their
states prior to standby mode. A reset or an
interrupt request if enabled cancels standby.
3.3 Sleep Mode
Writing to the
Sleep
bit in the
RegSysCntl1
register puts the EM6617-1 in sleep mode.
The oscillator stops and most functions of
the EM6617-1 are inactive. To be able to
write to the
Sleep
bit, the
SleepEn
bit in
RegSysCntl2
must first be set to "1". In
sleep mode only the voltage regulator and the reset input are active. The RAM data integrity is maintained.
Sleep mode may be canceled only by a high level of min 10μs at the Reset terminal or by the selected port A
input reset combination, if option
InpResSleep
in register
OPTFSelPB
is turned on.
Due to the cold-start characteristics of the oscillator, waking up from sleep mode may take some time to
guarantee stable oscillation. During sleep mode and the following start up the EM6617-1 is in reset state.
Waking up from sleep clears the
Sleep
flag but not the
SleepEn
bit. Inspecting the
SleepEn
allows to
determine if the EM6617-1 was powered up (
SleepEn
= "0") or woken up from sleep (
SleepEn
= "1").
Table 3.3.1. Internal State in Standby and Sleep Mode
Function
Oscillator
Oscillator Watchdog
Instruction Execution
Interrupt Functions
Registers and Flags
RAM Data
Option Registers
Timer & Counter
Logic Watchdog
I/O Port B and Serial Port
Standby
Active
Active
Stopped
Active
Retained
Retained
Retained
Active
Active
Active
Sleep
Stopped
Stopped
Stopped
Stopped
Reset
Retained
Retained
Reset
Reset
High Impedance,
Pull’s as defined in option register
No pull-downs and inputs deactivated
except if
InpResSleep
= "1"
Stopped (display off)
Active
High Impedance
Stopped
Active
Input Port A
Active
LCD
Active
Active
Active
Strobe Output
Buzzer Output
Voltage Level Detector
Reset Pin
Finishes ongoing measure, then stop
Active
Figure 5. Mode transition diagram
Active
Halt
instruction
Sleep bit
write
IRQ
Standby
Sleep
Reset=1
Reset=0
Reset=1
Reset=1
Reset
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