- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384283 > EDX5116ADSE-4D-E (ELPIDA MEMORY INC) 512M bits XDR⑩ DRAM PDF資料下載
參數(shù)資料
| 型號(hào)： | EDX5116ADSE-4D-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 512M bits XDR⑩ DRAM |
| 中文描述： | 32M X 16 RAMBUS, PBGA104 |
| 封裝： | ROHS COMPLIANT, FBGA-104 |
| 文件頁數(shù)： | 53/78頁 |
| 文件大?。?/td> | 3311K |
| 代理商： | EDX5116ADSE-4D-E |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁當(dāng)前第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁
Data Sheet E1033E30 (Ver. 3.0)
53
EDX5116ADSE
is that the COLM packet includes a M[7:0] field that indicates
the reserved bit pattern (for the eight bits of each byte) that
indicates that the byte is not to be written. This requires that
the alignment of bytes within the data packet be defined, and
also that the bit numbering within each byte be defined (note
that this was not necessary for the unmasked WR command).
In the figure, bytes are contained within a single DQ/DQN
pin pair
—
this is necessary so the dynamic width feature can be
supported. Thus, each pin pair carries two bytes of each data
packet. Byte[0] is transferred earlier than byte[16+0], and bit
[0] of each byte (corresponding to M[0]) is transferred first, fol-
lowed by the remaining bits in succession).
Figure 42
Write-Masked (WRM) Transac tion Example
T
0
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
t
CC
t
CWD
t
CYCLE
a1
WRM
a2
WRM
D(a2)
D(a1)
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
[1]
[0]
[2]
[4]
[3]
[5]
[7]
[6]
[8]
[10]
[9]
[11]
[13]
[12]
[14]
[15]
[1]
[0]
[2]
[4]
[3]
[5]
[7]
[6]
[8]
[10]
[9]
[11]
[13]
[12]
[14]
[15]
DQ0
DQN0
DQ15
DQN15
.
.
t
CAC
a1
RD
Q(a1)
Byte [0]
Bit- and Byte-number-
ing convention for write
and read data packets.
Byte [15]
Byte [16+15]
[1]
[0]
[2]
[4]
[3]
[5]
[7]
[6]
[8]
[10]
[9]
[11]
[13]
[12]
[14]
[15]
DQ1
DQN1
Byte [1]
Byte [16+0]
Byte [16+1]
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDX5116ADSE-3A-E | 512M bits XDR⑩ DRAM |
| EDZ20B | Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode |
| EDZ22B | LED 5MM 563NM HI GRN WATER CLEAR |
| EDZ24B | Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode |
| EDZ | Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDXSPECTRUMDAT/5962R8773901VDA | 制造商:Analog Devices 功能描述:SPECTRUM ANALYSIS - Literature |
| EDXSPECTRUMDATA/F8853801VGA | 制造商:Analog Devices 功能描述:DATA - Literature |
| EDXSPECTRUMDATA/R8512701VZA | 制造商:Analog Devices 功能描述:DATA - Literature |
| EDXSPECTRUMDATA/R9468002VHA | 制造商:Analog Devices 功能描述:DATA - Literature |
| EDXSPECTRUMDATA/R9468002VPA | 制造商:Analog Devices 功能描述:DATA - Literature |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。