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參數(shù)資料
| 型號： | EDX5116ADSE-4D-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 512M bits XDR⑩ DRAM |
| 中文描述： | 32M X 16 RAMBUS, PBGA104 |
| 封裝： | ROHS COMPLIANT, FBGA-104 |
| 文件頁數(shù)： | 35/78頁 |
| 文件大?。?/td> | 3311K |
| 代理商： | EDX5116ADSE-4D-E |
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Data Sheet E1033E30 (Ver. 3.0)
35
EDX5116ADSE
Figure 18
Configuration (CFG) Register
Figure 19
Power Management (PM) Register
Figure 20
Write Data S erial Load (WDS L) Control Register
7
6
5
4
3
2
WIDTH[2:0]
1
0
Read/write register
CFG[7:0] resets to 00000100
2
rsrv
WIDTH[2:0] - Device interface width field.
000
2
- Reserved.
001
2
- Reserved.
010
2
- x4 device width
011
2
- x8 device width
100
2
- x16 device width
101
2
, 110
2
, 111
2
- Reserved
SLE - Serial Load enable field.
0
2
- WDSL-path-to-memory disabled
1
2
- WDSL-path-to-memory enabled
Configuration Register
SADR[7:0]: 00000010
2
rsrv
SLE
rsrv
7
6
5
4
3
2
1
0
Read/write register
PM[7:0] resets to 00000000
2
PX
reserved
PX - Powerdown exit field.(write-one-only, read=zero)
0
2
- Powerdown entry - do not write zero - use PDN command
1
2
- Powerdown exit - write one to exit
PST[1:0] - Power state field (read-only).
00
2
- Powerdown (with self-refresh)
01
2
- Active/active-idle
10
2
- reserved
11
2
- reserved
PST[1:0]
Power Management Register
SADR[7:0]: 00000011
2
7
6
5
4
3
2
1
0
Read/write register
WDSL[7:0] resets to 00000000
2
WDSD[7:0] - Writing to this register places eight bits of data into
the serial-to-parallel conversion logic (the “Demux” block of
Figure 2). Writing to this register “2x16” times accumulates a full
“t
CC
” worth of write data. A subsequent WR command (with
SLE=1 in CFG register in Figure 18) will write this data (rather
than DQ data) to the sense amps of a memory bank. The shifting
order of the write data is shown in Table 10.
Write Data Serial Load Control Register
SADR[7:0]: 00000100
2
WDSD[7:0]
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