參數資料
型號: EDS6416CHTA-75-E
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 64M bits SDRAM (4M words x 16 bits)
中文描述: 4M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封裝: ROHS COMPLIANT, PLASTIC, TSOP2-54
文件頁數: 37/49頁
文件大?。?/td> 716K
代理商: EDS6416CHTA-75-E
EDS6416AHBH, EDS6416CHBH
Data Sheet E0442E40 (Ver. 4.0)
37
Bank active command interval
1. Same bank: The interval between the two bank active commands must be no less than tRC.
2. In the case of different bank active commands: The interval between the two bank active commands must be no
less than tRRD.
CLK
Command
Address
BS
Bank 0
Active
ACT
ROW
ACT
ROW
Bank 0
Active
tRC
Bank Active to Bank Active for Same Bank
CLK
Command
Address
BS
Bank 0
Active
Bank 3
Active
ACT
ROW:0
ACT
ROW:1
tRRD
Bank Active to Bank Active for Different Bank
Mode register set to Bank active command interval
The interval between setting the mode register and executing a bank active command must be no less than
l
MRD.
CLK
Command
Address
Mode
Register Set
Bank
Active
MRS
l
MRD
ACT
BS & ROW
OPCODE
Mode register set to Bank active command interval
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