
EDS5104ABTA, EDS5108ABTA, EDS5116ABTA
Preliminary Data Sheet E0250E10 (Ver. 1.0)
7
Test Conditions
Input and output timing reference levels: 1.4V
Input waveform and output load: See following figures
tT
2.4 V
0.4 V0.8 V
2.0 V
input
t
T
I/O
CL
Output load
Relationship Between Frequency and Minimum Latency
Parameter
-6B
-7A
-75
Frequency (MHz)
166
133
tCK (ns)
Symbol
6.0
7.5
7.5
Notes
Active command to column command
(same bank)
Active command to active command
(same bank)
Active command to precharge command
(same bank)
Precharge command to active command
(same bank)
Write recovery or data-in to precharge
command (same bank)
Active command to active command
(different bank)
Self refresh exit time
Last data in to active command
(Auto precharge, same bank)
lRCD
3
2
3
1
lRC
10
8
9
1
lRAS
7
6
6
1
lRP
3
2
3
1
lDPL
2
2
2
1
lRRD
2
2
2
1
lSREX
1
1
1
2
lDAL
5
4
5
= [lDPL + lRP]
Self refresh exit to command input
lSEC
10
8
9
= [lRC]
3
Precharge command to high impedance
(CL = 2)
(CL = 3)
Last data out to active command
(Auto precharge, same bank)
Last data out to precharge (early precharge)
(CL = 2)
(CL = 3)
lHZP
lHZP
—
3
2
3
2
3
lAPR
1
1
1
lEP
lEP
—
–2
–1
–2
–1
–2
Column command to column command
lCCD
1
1
1
Write command to data in latency
lWCD
0
0
0
DQM to data in
lDID
0
0
0
DQM to data out
lDOD
2
2
2
CKE to CLK disable
lCLE
1
1
1
Register set to active command
lMRD
2
2
2
/CS to command disable
lCDD
0
0
0
Power down exit to command input
lPEC
1
1
1
Notes: 1. IRCD to IRRD are recommended value.
2. Be valid [DESL] or [NOP] at next command of self refresh exit.
3. Except [DESL] and [NOP]