- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384282 > EDS5108ABTA-6B (ELPIDA MEMORY INC) 512M bits SDRAM PDF資料下載
參數(shù)資料
| 型號(hào)： | EDS5108ABTA-6B |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 512M bits SDRAM |
| 中文描述： | 64M X 8 SYNCHRONOUS DRAM, 5 ns, PDSO54 |
| 封裝： | PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 29/52頁 |
| 文件大小： | 564K |
| 代理商： | EDS5108ABTA-6B |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁當(dāng)前第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
EDS5104ABTA, EDS5108ABTA, EDS5116ABTA
Preliminary Data Sheet E0250E10 (Ver. 1.0)
29
Auto Precharge
Read with auto-precharge
In this operation, since precharge is automatically performed after completing a read operation, a precharge
command need not be executed after each read operation. The command executed for the same bank after the
execution of this command must be the bank active (ACT) command. In addition, an interval defined by lAPR is
required before execution of the next command.
[Clock cycle time]
/CAS latency
Precharge start cycle
3
2 cycle before the final data is output
2
1 cycle before the final data is output
CLK
lAPR
lRAS
lAPR
CL=2 Command
CL=3 Command
DQ
DQ
Note: Internal auto-precharge starts at the timing indicated by " ".
And an interval of tRAS (lRAS) is required between previous active (ACT) command and internal precharge " ".
ACT
READA
ACT
out3
out2
out1
out0
lRAS
ACT
READA
ACT
out3
out2
out1
out0
Burst Read (BL = 4)
Write with auto-precharge
In this operation, since precharge is automatically performed after completing a burst write or single write operation,
a precharge command need not be executed after each write operation. The command executed for the same bank
after the execution of this command must be the bank active (ACT) command. In addition, an interval of lDAL is
required between the final valid data input and input of next command.
CLK
Command
DQ
lDAL
I
RAS
ACT
WRITA
in0
in1
in2
in3
ACT
Note: Internal auto-precharge starts at the timing indicated by " ".
and an interval of tRAS (lRAS) is required between previous active (ACT) command
and internal precharge " ".
Burst Write (BL = 4)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDS5104ABTA-75 | 512M bits SDRAM |
| EDS5108ABTA-75 | 512M bits SDRAM |
| EDS5104ABTA-7A | 512M bits SDRAM |
| EDS5108ABTA-7A | 512M bits SDRAM |
| EDS5108ABTA | 512M bits SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDS5108ABTA-75 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits SDRAM |
| EDS5108ABTA-7A | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits SDRAM |
| EDS5116ABTA | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits SDRAM |
| EDS5116ABTA-6B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits SDRAM |
| EDS5116ABTA-75 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits SDRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。