
EDS2516AFTA
Data Sheet E0984E20 (Ver. 2.0)
7
AC Characteristics (TA = 0 to +70
°
C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V)
-6B
-75
Parameter
System clock cycle time
(CL = 2)
Symbol
min.
max.
min.
max.
Unit
Notes
tCK
10
—
10
—
ns
1
(CL = 3)
tCK
6
—
7.5
—
ns
1
CLK high pulse width
tCH
2.5
—
2.5
—
ns
1, 5
CLK low pulse width
tCL
2.5
—
2.5
—
ns
1, 5
Access time from CLK
tAC
—
5.4
—
5.4
1, 2, 5
Data-out hold time
tOH
3
—
3
—
ns
1, 2, 5
CLK to Data-out low impedance
tLZ
0
—
0
—
ns
1, 2, 3, 5
CLK to Data-out high impedance
tHZ
—
5.4
—
5.4
ns
1, 4
Input setup time
tSI
1.5
—
1.5
—
ns
1, 5
Input hold time
tHI
0.8
—
0.8
—
ns
1, 5
Ref/Active to Ref/Active command period tRC
60
—
67.5
—
ns
1
Active to Precharge command period
tRAS
42
120000
45
120000
ns
1
Active command to column command
(same bank)
tRCD
18
—
20
—
ns
1
Precharge to active command period
tRP
18
—
20
—
ns
1
Write recovery or data-in to precharge
lead time
tDPL
12
—
15
—
ns
1
Last data into active latency
tDAL
2CLK + 18ns —
2CLK + 20ns —
Active (a) to Active (b) command period
tRRD
12
—
15
—
ns
1
Transition time (rise and fall)
tT
0.5
5
0.5
5
ns
Refresh period
(8192 refresh cycles)
Notes: 1. AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 1.4V.
2. Access time is measured at 1.4V. Load condition is CL = 50pF.
3. tLZ (min.) defines the time at which the outputs achieves the low impedance state.
4. tHZ (max.) defines the time at which the outputs achieves the high impedance state.
5. If tT
≥
1ns, each parameters is changed as follows;
tAC, tOH, tLZ: should be added (tT (rise)/2 – 0.5)
tCH, tCL, tSI, tHI: should be added {(tT (rise) + tT (fall))/2 – 1}
tREF
—
64
—
64
ms