參數(shù)資料
型號(hào): EDS2516AFTA
廠商: Elpida Memory, Inc.
英文描述: 256M bits SDRAM
中文描述: 256M比特內(nèi)存
文件頁(yè)數(shù): 32/50頁(yè)
文件大小: 603K
代理商: EDS2516AFTA
EDS2516AFTA
Data Sheet E0984E20 (Ver. 2.0)
32
Read command to Write command interval
1. Same bank, same ROW address: When the write command is executed at the same ROW address of the same
bank as the preceding read command, the write command can be performed after an interval of no less than 1
clock. However, UDQM and LDQM must be set High so that the output buffer becomes High-Z before data input.
CLK
Command
DQ (output)
in B2
in B3
READ
WRIT
in B0
in B1
High-Z
DQ (input)
CL=2
CL=3
UDQM
LDQM
BL = 4
Burst write
READ to WRITE Command Interval (1)
CLK
Command
DQ
READ
WRIT
CL=2
CL=3
UDQM
LDQM
2 clock
out
out
out
out
out
in
in
in
in
in
in
in
in
READ to WRITE Command Interval (2)
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be
executed; it is necessary to separate the two commands with a precharge command and a bank active
command.
3. Different bank: When the bank changes, the write command can be performed after an interval of no less than 1
cycle, provided that the other bank is in the bank active state. However, UDQM and LDQM must be set High so
that the output buffer becomes High-Z before data input.
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