參數(shù)資料
型號(hào): EDS1232CABB
廠商: Elpida Memory, Inc.
英文描述: 128M bits SDRAM
中文描述: 128兆位內(nèi)存
文件頁(yè)數(shù): 12/55頁(yè)
文件大小: 564K
代理商: EDS1232CABB
EDS1232CABB, EDS1232CATA
Preliminary Data Sheet E0247E40 (Ver. 4.0)
12
Command Operation
Mode register set command (/CS, /RAS, /CAS, /WE)
The Synchronous DRAM has a mode register that defines how the device operates. In this command, A0 through
A11 are the data input pins. After power on, the mode register set command must be executed to initialize the
device. The mode register can be set only when all banks are in idle state. During 2CLK (tRSC) following this
command, the Synchronous DRAM cannot accept any other commands.
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0, BA1
(Bank select)
Mode Register Set Command
Activate command (/CS, /RAS = Low, /CAS, /WE = High)
The Synchronous DRAM has four banks, each with 4,096 rows. This command activates the bank selected by BA0
and BA1 and a row address selected by A0 through A11. This command corresponds to a conventional DRAM's
/RAS falling.
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
(Bank select)
Row
Row
Row Address Strobe and Bank Activate Command
相關(guān)PDF資料
PDF描述
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