參數(shù)資料
型號(hào)： EDS1232AATA-75L-E
廠商： ELPIDA MEMORY INC
元件分類(lèi)： DRAM
英文描述： 128M bits SDRAM (4M words x 32 bits)
中文描述： 4M X 32 SYNCHRONOUS DRAM, 5.4 ns, PDSO86
封裝： ROHS COMPLIANT, PLASTIC, TSOP2-86
文件頁(yè)數(shù)： 9/55頁(yè)
文件大?。?/td> 564K
代理商： EDS1232AATA-75L-E
EDS1232CABB, EDS1232CATA
Preliminary Data Sheet E0247E40 (Ver. 4.0)
9
Relationship Between Frequency and Minimum Latency
Parameter
-75
-1A
Frequency (MHz)
133
100
100
77
tCK (ns)
Symbol
7.5
10
10
13
Notes
Active command to column command
(same bank)
Active command to active command
(same bank)
Active command to precharge command
(same bank)
Precharge command to active command
(same bank)
Write recovery or data-in to precharge
command (same bank)
Active command to active command
(different bank)
Self refresh exit time
Last data in to active command
(Auto precharge, same bank)
lRCD
3
2
2
2
1
lRC
9
7
7
6
1
lRAS
6
5
5
4
1
lRP
3
2
2
2
1
lDPL
2
2
2
2
1
lRRD
2
2
2
2
1
lSREX
1
1
1
1
2
lDAL
5
4
4
4
= [lDPL + lRP]
Self refresh exit to command input
lSEC
9
7
7
6
= [lRC]
3
Precharge command to high impedance
(CL = 2)
(CL = 3)
Last data out to active command
(auto precharge) (same bank)
Last data out to precharge
(early precharge)
(CL = 2)
(CL = 3)
lHZP
2
2
2
lHZP
3
3
3
3
lAPR
1
1
1
1
lEP
–1
–1
–1
lEP
–2
–2
–2
–2
Column command to column command
lCCD
1
1
1
1
Write command to data in latency
lWCD
0
0
0
0
DQM to data in
lDID
0
0
0
0
DQM to data out
lDOD
2
2
2
2
CKE to CLK disable
lCLE
1
1
1
1
Register set to active command
lMRD
2
2
2
2
/CS to command disable
lCDD
0
0
0
0
Power down exit to command input
lPEC
1
1
1
1
Notes: 1. IRCD to IRRD are recommended value.
2. Be valid [DESL] or [NOP] at next command of self refresh exit.
3. Except [DESL] and [NOP]
相關(guān)PDF資料
PDF描述
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參數(shù)描述
EDS1232AATA-75MI 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:128M bits SDRAM WTR (Wide Temperature Range)
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EDS1232AATA-TI 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:128M bits SDRAM WTR (Wide Temperature Range)
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