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參數(shù)資料
| 型號： | EDI88130LPS17CM |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | SRAM |
| 英文描述： | 128K X 8 STANDARD SRAM, 17 ns, CDIP32 |
| 封裝： | 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-32 |
| 文件頁數(shù)： | 4/9頁 |
| 文件大小： | 499K |
| 代理商： | EDI88130LPS17CM |
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
EDI88130CS
March 2002
Rev. 11
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
AC CHARACTERISTICS – WRITE CYCLE (15 to 20ns)
V
CC
= 5.0V, Vss = 0V, -55°C
≤
T
A
≤
+125°C
Symbol
JEDEC
Alt.
Min
t
AVAV
t
WC
15
t
E1LWH
t
E1LE1H
t
E2HWH
t
E2HE2L
t
CW
12
t
AVWL
t
AVE1L
t
AVE2H
t
AS
0
t
AVWH
t
AW
12
t
WLWH
t
WLE1H
t
WLE2L
t
WP
12
t
WHAX
t
E1HAX
t
E2LAX
t
WR
0
t
WHDX
t
E1HDX
t
E2LDX
t
DH
0
t
WLQZ
t
WHZ
0
t
DVWH
t
DVE1H
t
DVE2L
t
DW
7
t
WHQX
t
WLZ
3
1. This parameter is guaranteed by design but not tested.
Parameter
Write Cycle Time
Chip Enable to End of Write
15ns*
17ns
20ns
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Max
Min
17
13
13
13
13
0
0
0
13
13
13
13
0
0
0
0
0
0
0
8
8
8
3
Max
Min
20
15
15
15
15
0
0
0
15
15
15
15
0
0
0
0
0
0
0
10
10
10
3
Max
t
CW
t
CW
t
CW
12
12
Address Setup Time
t
AS
t
AS
0
0
Address Valid to End of Write
Write Pulse Width
t
WP
t
WP
12
Write Recovery Time
t
WR
t
WR
0
0
Data Hold Time
t
DH
t
DH
0
0
Write to Output in High Z (1)
Data to Write Time
7
8
8
t
DW
t
DW
7
7
Output Active from End of Write (1)
AC CHARACTERISTICS – WRITE CYCLE (25 to 55ns)
V
CC
= 5.0V, Vss = 0V, -55°C
≤
T
A
≤
+125°C
Symbol
JEDEC
Alt.
Min
t
AVAV
t
WC
25
t
E1LWH
t
E1LE1H
t
E2HWH
t
E2HE2L
t
CW
t
AVWL
t
AVE1L
t
AVE2H
t
AS
0
t
AVWH
t
AVEH
t
AW
20
t
WLWH
t
WLE1H
t
WLE2L
t
WP
20
t
WHAX
t
E1HAX
t
E2LAX
t
WR
0
t
WHDX
t
E1HDX
t
E2LDX
t
DH
0
t
WLQZ
t
WHZ
0
t
DVWH
t
DVE1H
t
DVE2L
t
DW
15
t
WHQX
t
WLZ
3
1. This parameter is guaranteed by design but not tested.
25ns
35ns
45ns
55ns
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Write Cycle Time
Chip Enable to End of Write
Max
Min
35
25
Max
Min
45
35
Max
Min
55
45
Max
t
CW
t
CW
t
CW
20
16
16
16
20
20
20
25
25
25
40
40
40
Address Setup Time
t
AS
t
AS
0
0
0
0
0
0
0
0
0
0
0
Address Valid to End of Write
t
AW
20
25
25
30
30
30
0
0
0
0
0
0
0
20
20
20
3
35
35
30
30
30
5
5
5
0
0
0
0
20
20
20
3
45
45
35
35
35
5
5
5
0
0
0
0
25
25
25
3
Write Pulse Width
t
WP
t
WP
20
Write Recovery Time
t
WR
t
WR
0
0
Data Hold Time
t
DH
t
DH
0
0
Write to Output in High Z (1)
Data to Write Time
10
13
15
20
t
DW
t
DW
15
Output Active from End of Write (1)
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