參數(shù)資料
型號: EDGE4707B
英文描述: Edge4707B PPMU Settling Time & Stability (224k)
中文描述: Edge4707B PPMU建立時間
文件頁數(shù): 7/13頁
文件大?。?/td> 224K
代理商: EDGE4707B
3
TEST AND MEASUREMENT PRODUCTS
www .semtech.com
PMU-A2
Edge4707B PPMU
Settling Time and Stability
Revision 1 / November 8, 2002
on the FORCE output should be kept to a minimum
whenever possible. As will be shown later, minimizing this
capacitance will also help shorten the settling time for
small voltage steps.
Limiting the size of the input voltage steps will almost
always keep the output from going to the rail. However,
limiting this is not always possible. An alternative is to
limit the slew rate of the input signal so it is not faster
than the slew rate of the output signal. This can be done
by changing the value of the COMP3 capacitor shown in
the Figure 1 block diagram. This capacitor, along with the
40 K
resistor in series with the input, creates an R-C
time constant which effectively limits the slew rate of the
signal going into the driver amp. The slew rates at the
force output on each of the ranges, with varying
compensation capacitors, is shown in Figures 2 through
5. Since the settling time on the lower current ranges
(A and B) is much longer than the rail recovery time,
keeping the output from going to the rail is less important
on these ranges. It is more important to limit the input
slew rate when using the higher current ranges, since this
will give the greatest settling time improvement.
The maximum slew rates with a ~100pF load capacitance
for each range can be found from the data in Figures 2
through 5. On Ranges C and D the maximum slew rates
are about 1.1V/
s. If a 100pF capacitor is used for
COMP3, then the maximum input slew rate will be
2.5V/
s, and the average slew rate will be 1.25V/s.
100pF is the recommended value for keeping the output
from going to the rail on these ranges. This is the
recommended value for this compensation capacitor for
most systems.
Ranges A and B have maximum slew rates of about 0.55V/
s. To keep the output from going to the rail on these
ranges, the COMP3 capacitor should be increased to about
220pF. Since the rail recovery time on these ranges is
significantly less than the settling time for most situations,
setting COMP3 to this large a value is normally not
recommended since this will slow down the performance
on the higher current ranges.
Note that the above calculations are for a relatively small
output load capacitance (eg. 100pF). With larger output
load capacitance, the output can still go to the rail due to
overshoot and ringing. This will be covered in more detail
in the Stability Section below.
10V step Force output settling characteristic
Range A
-2
0
2
4
6
8
10
0.0E+00
5.0E-05
1.0E-04
1.5E-04
2.0E-04
2.5E-04
3.0E-04
3.5E-04
4.0E-04
Time (sec)
C1-2=0pF, C4=0pF
c1-2=0pF, C4=47pF
c1-2=47pF, c4=0pF
c1-2=47pF, c4=47pF
c1-2=100pF, c4=100pF
Figure 2. Range A (2
A) Force Output Settling in Force Voltage Mode (CLOAD = 108 pF)
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