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參數(shù)資料
| 型號： | EDGE4707B |
| 英文描述： | Edge4707B PPMU Settling Time & Stability (224k) |
| 中文描述： | Edge4707B PPMU建立時間 |
| 文件頁數(shù)： | 4/13頁 |
| 文件大小： | 224K |
| 代理商： | EDGE4707B |
12
TEST AND MEASUREMENT PRODUCTS
www .semtech.com
PMU-A2
Edge4707B PPMU
Settling Time and Stability
Revision 1 / November 8, 2002
Example 2:
The test system needs to be designed with compensation
capacitors of COMP1-2=22pF and COMP4=47pF in order
to get the fastest settling times under most circumstances.
However, the user may put a bypass capacitor next to the
DUT pin as large as 0.01
f. With this capacitance range,
what should be the maximum voltage step to keep the
overshoot less than 700mV?
Figure 8 indicates that Range D may have as much as
2.5V of overshoot (with a 10V step) within this range of
load capacitance. Figure 7 indicates that the change in
overshoot is proportional to voltage step size, but not
exactly linear. So limiting the step size to 2V will likely
limit the maximum overshoot to 0.5V, but this will have to
be verified using an EVM board or with the final circuit.
Summary
The bottom line is that there will always be a trade-off
between fast settling time, maximum accuracy and keeping
overshoot and ringing low enough so there is no risk of
damaging DUTs. The final decision on appropriate
compensation capacitors for a given design should take
all of these factors into account when determining the
optimum compensation for a particular design.
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