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參數(shù)資料
| 型號： | EDE5116AJBG-8E-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 512M bits DDR2 SDRAM |
| 中文描述： | 32M X 16 DDR DRAM, 0.4 ns, PBGA84 |
| 封裝： | ROHS COMPLIANT, FBGA-84 |
| 文件頁數(shù)： | 36/77頁 |
| 文件大?。?/td> | 589K |
| 代理商： | EDE5116AJBG-8E-E |
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EDE5108AJBG, EDE5116AJBG
Preliminary Data Sheet E1044E20 (Ver. 2.0)
36
Operation of DDR2 SDRAM
Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue
for the fixed burst length of four or eight in a programmed sequence. Accesses begin with the registration of an
active command, which is then followed by a read or write command. The address bits registered coincident with
the active command is used to select the bank and row to be accessed (BA0, BA1 select the bank; A0 to A13 select
the row). The address bits registered coincident with the read or write command are used to select the starting
column location for the burst access and to determine if the auto precharge command is to be issued.
Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed information
covering device initialization; register definition, command descriptions and device operation.
Power On and Initialization
DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than
those specified may result in undefined operation.
Power-Up and Initialization Sequence
The following sequence is required for power up and initialization.
1. Apply power and attempt to maintain CKE below 0.2
×
VDDQ and ODT *
1
at a low state (all other inputs may be
undefined.)
VDD, VDDL and VDDQ are driven from a single power converter output, AND
VTT is limited to 0.95V max, AND
VREF tracks VDDQ/2.
or
Apply VDD before or at the same time as VDDL.
Apply VDDL before or at the same time as VDDQ.
Apply VDDQ before or at the same time as VTT and VREF.
at least one of these two sets of conditions must be met.
2. Start clock and maintain stable condition.
3. For the minimum of 200
μ
s after stable power and clock (CK, /CK), then apply [NOP] or [DESL] and take CKE
high.
4. Wait minimum of 400ns then issue precharge all command. [NOP] or [DESL] applied during 400ns period.
5. Issue EMRS (2) command. (To issue EMRS (2) command, provide low to BA0, high to BA1.)
6. Issue EMRS (3) command. (To issue EMRS (3) command, high to BA0 and BA1.)
7. Issue EMRS to enable DLL. (To issue DLL enable command, provide low to A0, high to BA0 and low to BA1 and
A13.)
8. Issue a mode register set command for DLL reset.
(To issue DLL reset command, provide high to A8 and low to BA0, BA1 and A13.)
9. Issue precharge all command.
10. Issue 2 or more auto-refresh commands.
11. Issue a mode register set command with low to A8 to initialize device operation. (i.e. to program operating
parameters without resetting the DLL.)
12. At least 200 clocks after step 8, execute OCD calibration (Off Chip Driver impedance adjustment). If OCD
calibration is not used, EMRS OCD default command (A9 = A8 = A7 = 1) followed by EMRS OCD calibration
mode exit command (A9 = A8 = A7 = 0) must be issued with other operating parameters of EMRS.
13. The DDR2 SDRAM is now ready for normal operation.
Note: 1. To guarantee ODT off, VREF must be valid and a low level must be applied to the ODT pin.
EMRS
EMRS(3)
MRS
tMRD
tMRD
tMRD
200 cycles (min)
tMRD
tMRD
tRP
tRFC
tRFC
PALL
MRS
REF
REF
EMRS
DLL enable
DLL reset
Flowchart
coAny
EMRS
OCD cali exit
tOIT
OCD default
EMRS(2)
Command
PALL
tRP
400ns
NOP
CK
/CK
CKE
tCH tCL
tIS
Power up and Initialization Sequence
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDE5116AJBG-LI | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM WTR (Wide Temperature Range) |
| EDE5116AJSE | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5116AJSE-6E-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5116AJSE-6ELI-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5116AJSE-8E-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
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