參數(shù)資料
型號(hào)： EDE5116AJBG-8E-E
廠商： ELPIDA MEMORY INC
元件分類： DRAM
英文描述： 512M bits DDR2 SDRAM
中文描述： 32M X 16 DDR DRAM, 0.4 ns, PBGA84
封裝： ROHS COMPLIANT, FBGA-84
文件頁(yè)數(shù)： 34/77頁(yè)
文件大小： 589K
代理商： EDE5116AJBG-8E-E
EDE5108AJBG, EDE5116AJBG
Preliminary Data Sheet E1044E20 (Ver. 2.0)
34
8. The minimum delay from the read, write and precharge command to the precharge command to the same
bank is summarized below.
[Precharge and Auto Precharge Clarification]
From command
To command
Minimum delay between “From
command” to “To Command“
Units
Notes
Read
Precharge (to same bank as read)
AL + (BL/2) + Max.(RTP, 2)
2
tCK
a, b
Precharge all
AL + (BL/2) + Max.(RTP, 2)
2
tCK
a, b
Read w/AP
Precharge (to same bank as read w/AP)
AL + (BL/2) + Max.(RTP, 2)
2
tCK
a, b
Precharge all
AL + (BL/2) + Max.(RTP, 2)
2
tCK
a, b
Write
Precharge (to same bank as write)
WL + (BL/2) + tWR
tCK
b
Precharge all
WL + (BL/2) + tWR
tCK
b
Write w/AP
Precharge (to same bank as write w/AP)
WL + (BL/2) + WR
tCK
b
Precharge all
WL + (BL/2) + WR
tCK
b
Precharge
Precharge (to same bank as precharge)
1
tCK
b
Precharge all
1
tCK
b
Precharge all
Precharge
1
tCK
b
Precharge all
1
tCK
b
a. RTP[cycles] = RU{ tRTP[ns] / tCK[ns] }, where RU stands for round up.
tCK(avg) should be used in place of tCK for DDR2-667/800.
b. For a given bank, the precharge period should be counted from the latest precharge command, either one
bank precharge or precharge all, issued to that bank. The precharge period is satisfied after tRP
depending on the latest precharge command issued to that bank.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EDE5116AJBG-LI 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM WTR (Wide Temperature Range)
EDE5116AJSE 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM
EDE5116AJSE-6E-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM
EDE5116AJSE-6ELI-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM
EDE5116AJSE-8E-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM
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