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| 型號： | EDE5108AJBG |
| 廠商： | Elpida Memory, Inc. |
| 英文描述： | 512M bits DDR2 SDRAM |
| 中文描述： | 512M比特DDR2 SDRAM內(nèi)存 |
| 文件頁數(shù)： | 18/77頁 |
| 文件大小： | 589K |
| 代理商： | EDE5108AJBG |
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EDE5108AJBG, EDE5116AJBG
Preliminary Data Sheet E1044E20 (Ver. 2.0)
18
Clock Jitter [DDR2-800, 667]
-8E
-6E
Frequency (Mbps)
800
667
Parameter
Symbol
min.
max.
min.
max.
Unit
Notes
Average clock period
tCK (avg)
2500
8000
3000
8000
ps
1
Clock period jitter
Clock period jitter during
DLL locking period
Cycle to cycle period jitter
Cycle to cycle clock period jitter
during DLL locking period
Cumulative error across 2 cycles
tJIT (per)
tJIT
(per, lck)
tJIT (cc)
100
100
125
125
ps
5
80
80
100
100
ps
5
200
250
ps
6
tJIT (cc, lck)
160
200
ps
6
tERR (2per)
150
150
175
175
ps
7
Cumulative error across 3 cycles
tERR (3per)
175
175
225
225
ps
7
Cumulative error across 4 cycles
tERR (4per)
200
200
250
250
ps
7
Cumulative error across 5 cycles
Cumulative error across
n=6,7,8,9,10 cycles
Cumulative error across
n=11, 12,…49,50 cycles
Average high pulse width
tERR (5per)
200
tERR
(6-10per)
tERR
(11-50per)
tCH (avg)
200
250
250
ps
7
300
300
350
350
ps
7
450
450
450
450
ps
7
0.48
0.52
0.48
0.52
tCK (avg) 2
Average low pulse width
tCL (avg)
0.48
0.52
0.48
0.52
tCK (avg) 3
Duty cycle jitter
tJIT (duty)
100
100
125
125
ps
4
Notes: 1. tCK (avg) is calculated as the average clock period across any consecutive 200cycle window.
N
tCKj
avg
tCK
=
∑
=
1
)
(
N = 200
2. tCH (avg) is defined as the average high pulse width, as calculated across any consecutive 200 high
pulses.
))
(
(
)
(
1
avg
tCK
N
tCHj
avg
tCH
N
j
×
=
∑
=
N = 200
3. tCL (avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses.
))
(
(
)
(
1
avg
tCK
N
tCLj
avg
tCL
N
j
×
=
∑
=
N = 200
4. tJIT (duty) is defined as the cumulative set of tCH jitter and tCL jitter. tCH jitter is the largest deviation of
any single tCH from tCH (avg). tCL jitter is the largest deviation of any single tCL from tCL (avg).
tJIT (duty) is not subject to production test.
tJIT (duty) = Min./Max. of {tJIT (CH), tJIT (CL)}, where:
tJIT (CH) = {tCH
j
- tCH (avg) where j = 1 to 200}
tJIT (CL) = {tCL
j
tCL (avg) where j = 1 to 200}
5. tJIT (per) is defined as the largest deviation of any single tCK from tCK (avg).
tJIT (per) = Min./Max. of { tCK
j
tCK (avg) where j = 1 to 200}
tJIT (per) defines the single period jitter when the DLL is already locked. tJIT (per, lck) uses the same
definition for single period jitter, during the DLL locking period only. tJIT (per) and tJIT (per, lck) are not
subject to production test.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDE5108AJBG-6E-E | 512M bits DDR2 SDRAM |
| EDE5108AJBG-8E-E | 512M bits DDR2 SDRAM |
| EDE5116AJBG | 512M bits DDR2 SDRAM |
| EDE5116AJBG-6E-E | 512M bits DDR2 SDRAM |
| EDE5116AJBG-8E-E | 512M bits DDR2 SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDE5108AJBG-1J | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5108AJBG-1J-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5108AJBG-6E-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5108AJBG-8E-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5108AJSE | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
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